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resources:fpga:xilinx:interposer:ad5669 [20 Feb 2012 11:09] – Approved Andrei Cozma | resources:fpga:xilinx:interposer:ad5669 [09 Jan 2021 00:48] (current) – user interwiki links Robin Getz | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
- | For component evaluation and performance purposes, as opposed to quick prototyping, | + | {{page>common_sdp}} |
- | * a controller board, like the **[[resources/ | + | |
- | * a compatible Analog Devices SDP [[adi>sdp# | + | |
- | * corresponding PC software | + | |
- | The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. | + | |
Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5669RSDZ** Evaluation Board. | Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5669RSDZ** Evaluation Board. | ||
- | |||
- | Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5669R** Evaluation Board. | ||
{{ : | {{ : | ||
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* [[adi> | * [[adi> | ||
* {{: | * {{: | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
- | * [[http:// | + | |
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Hardware ===== | ===== Required Hardware ===== | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
* FMC-SDP adapter board | * FMC-SDP adapter board | ||
* **EVAL-AD5669R** evaluation board | * **EVAL-AD5669R** evaluation board | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD5669R reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **AD5669R Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **AD5669R Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | + | ||
- | ===== Demonstration Project User Interface | + | |
- | + | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5669** evaluation board. | + | |
- | + | ||
- | {{ : | + | |
- | + | ||
- | **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **// | + | |
- | + | ||
- | **Section B** is used to write/ | + | |
- | **Section C** is used to display | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage | ||
+ | </ | ||
- | **Section D** is used to control | + | |
+ | | ||
- | **Section E** is used to change | + | <WRAP round important 80%> |
+ | \\ | ||
+ | To power on the EVAL-AD5669R evaluation board, you need to provide +5V supply voltage | ||
+ | </ | ||
- | **Section F** is used to select | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented in this version of EVAL-AD5669R reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **reset!** | Makes a power-on reset. | | ||
+ | | **powerMode=** | Selects a given power mode for selected DAC. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ power mode:\\ 0 - normal operation.\\ 1 - 1KOhm to GND.\\ 2 - 100KOhms to GND.\\ 3 - three-state. | | ||
+ | | **powerMode? | ||
+ | | **intRef=** | Turns on/off the internal reference. Accepted values:\\ 0 - turns off the internal reference.\\ 1 - turns on the internal reference. | | ||
+ | | **intRef?** | Displays the status | ||
+ | | **loadN=** | Loads selected DAC register with a given value. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ 15 - all DACs.\\ value:\\ 0 .. 65535 - value to be written in register. | | ||
+ | | **updateN** | Updates | ||
+ | | **loadNUpdateN** | Loads and updates the selected DAC with a given value. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ 15 - all DACs.\\ value:\\ 0 .. 65535 - value to be written in register. | | ||
+ | | **loadNUpdateAll** | Loads the selected DAC with a given value and updates all DACs. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ 15 - all DACs.\\ value:\\ 0 .. 65535 - value to be written in register. | | ||
+ | | **enLdacPin=** | Enables/ | ||
+ | | **enLdacPin? | ||
+ | | **clrCode=** | Loads Clear Code Register with specific clear code.\\ Accepted values:\\ 0 - clears code to zero scale when CLR pin goes from high to low.\\ 1 - clears code to midscale when CLR pin goes from high to low.\\ 2 - clears code to full scale when CLR pin goes from high to low.\\ 3 - no operation. | | ||
+ | | **clrCode? | ||
+ | | **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. | | ||
+ | | **ldacPin? | ||
+ | | **clrPin=** | Sets the output value of CLR pin. Accepted values:\\ 0 - sets CLR pin low.\\ 1 - sets CLR pin high.(default) | | ||
+ | | **clrPin?** | Displays the value of CLR pin. | | ||
- | **Section G** is used to control | + | Commands can be executed using a serial terminal connected |
- | ===== Troubleshooting | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
+ | ===== Software Project Setup ===== | ||
+ | {{page> | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | ||
- | * Check that the evaluation board is powered as instructed in the board' | ||
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | ||
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | ||
====== More information ====== | ====== More information ====== | ||
- | * [[ez>community/ | + | {{page>ez_common}} |