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resources:fpga:xilinx:interposer:ad5669 [20 Feb 2012 11:04] – created Andrei Cozmaresources:fpga:xilinx:interposer:ad5669 [09 Jan 2021 00:48] (current) – user interwiki links Robin Getz
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>AD5669R|EVAL-AD5669RSDZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5669RSDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>AD5669R|EVAL-AD5669RSDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5669RSDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :resources:fpga:xilinx:interposer:ad5669.jpg?400 }} {{ :resources:fpga:xilinx:interposer:ad5669.jpg?400 }}
  
-For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: +{{page>common_sdp}}
-  * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)** +
-  * a compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]] +
-  * corresponding PC software +
-The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software.  Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.+
  
 Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5669RSDZ** Evaluation Board. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5669RSDZ** Evaluation Board.
- 
-Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5669R** Evaluation Board. 
  
 {{ :resources:fpga:altera:bemicro:ad5669r_sdp1z.png?400 }} {{ :resources:fpga:altera:bemicro:ad5669r_sdp1z.png?400 }}
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   * [[adi>AD5669R|AD5669R Product Info]] - pricing, samples, datasheet   * [[adi>AD5669R|AD5669R Product Info]] - pricing, samples, datasheet
   * {{:resources:fpga:altera:bemicro:ad5669r_ug.pdf|EVAL-AD5669 evaluation board user guide}}   * {{:resources:fpga:altera:bemicro:ad5669r_ug.pdf|EVAL-AD5669 evaluation board user guide}}
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] +  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]]+
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Hardware ===== ===== Required Hardware =====
  
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
   * FMC-SDP adapter board   * FMC-SDP adapter board
   * **EVAL-AD5669R** evaluation board   * **EVAL-AD5669R** evaluation board
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.6. 
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200. 
 +  * The EVAL-AD5669R reference project for Xilinx KC705 FPGA.
  
 ===== Downloads ===== ===== Downloads =====
- +<WRAP round download 80%> 
-  * {{:resources:fpga:xilinx:interposer:ad5669_evalboard.zip|Reference Design Files}} +\\ 
- +  * **AD5669R Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5629R 
-The following table presents a short description the reference design archive contents. +  * **AD5669R Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5629R 
- +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common 
-^ **Folder** ^ **Description** ^ +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +</WRAP>
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | +
 ====== Run the Demonstration Project ====== ====== Run the Demonstration Project ======
  
-{{page>ucprobe_common}} +===== Hardware setup =====
- +
-===== Demonstration Project User Interface ===== +
- +
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5669** evaluation board. +
- +
-{{ :resources:fpga:altera:bemicro:ad5669r_interface.png?700 }} +
- +
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. +
- +
-**Section B** is used to write/update DAC channels. The horizontal slider represents the data value and the vertical slider represents the DAC channel. An operation can be chosen by pressing one of the four buttons.+
  
-**Section C** is used to display the output value of any DAC channel.+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-**Section D** is used to control the LDAC and CLR pins of the AD5669R.+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-**Section E** is used to change the clear code value,to reset the DAC to the power-on reset code and to turn on or off the internal reference.+<WRAP round important 80%> 
 +\\ 
 +To power on the EVAL-AD5669R evaluation board, you need to provide +5V supply voltage to J2 connector on the board. 
 +</WRAP>
  
-**Section F** is used to select one of four separate modes of operations. Any or all DACs can be powered down by pressing the corresponding button and selecting an operating mode. After any change of the buttons position is necessary to move the slider to the desired position.+===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-AD5669R reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **reset!** | Makes a power-on reset. | 
 +| **powerMode=** | Selects a given power mode for selected DAC. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ power mode:\\ 0 - normal operation.\\ 1 - 1KOhm to GND.\\ 2 - 100KOhms to GND.\\ 3 - three-state. | 
 +| **powerMode?** | Displays the power mode for one selected DAC. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H. | 
 +| **intRef=** | Turns on/off the internal reference. Accepted values:\\ 0 - turns off the internal reference.\\ 1 - turns on the internal reference. | 
 +| **intRef?** | Displays the status of the internal reference. | 
 +| **loadN=** | Loads selected DAC register with a given value. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ 15 - all DACs.\\ value:\\ 0 .. 65535 - value to be written in register. | 
 +| **updateN** | Updates the selected DAC with the last value written in register. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ 15 - all DACs.\\ value:\\ 0 .. 65535 - value to be written in register. | 
 +| **loadNUpdateN** | Loads and updates the selected DAC with a given value. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ 15 - all DACs.\\ value:\\ 0 .. 65535 - value to be written in register. | 
 +| **loadNUpdateAll** | Loads the selected DAC with a given value and updates all DACs. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ 15 - all DACs.\\ value:\\ 0 .. 65535 - value to be written in register. | 
 +| **enLdacPin=** | Enables/Disables the LDAC pin for selected DAC. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ value:\\ 1 - disable LDAC pin.\\ 0 - enable LDAC pin. | 
 +| **enLdacPin?** | Displays the status(enabled or disabled) of the LDAC pin for a selected DAC. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H. | 
 +| **clrCode=** | Loads Clear Code Register with specific clear code.\\ Accepted values:\\ 0 - clears code to zero scale when CLR pin goes from high to low.\\ 1 - clears code to midscale when CLR pin goes from high to low.\\ 2 - clears code to full scale when CLR pin goes from high to low.\\ 3 - no operation. | 
 +| **clrCode?** | Displays the active clear code. | 
 +| **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. | 
 +| **ldacPin?** | Displays the value of LDAC pin. | 
 +| **clrPin=** | Sets the output value of CLR pin. Accepted values:\\ 0 - sets CLR pin low.\\ 1 - sets CLR pin high.(default) | 
 +| **clrPin?** | Displays the value of CLR pin. |
  
-**Section G** is used to control the LDAC register. If the button is not pressed for a DAC channel means that this channel's update is controlled by the LDAC pin. After any change of the buttons position is necessary to press the **//Load LDAC Reg.//** button.+Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
  
-===== Troubleshooting =====+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }} 
 +===== Software Project Setup ===== 
 +{{page>import_workspace}}
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: 
-  * Check that the evaluation board is powered as instructed in the board's user guide. 
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. 
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. 
  
 ====== More information ====== ====== More information ======
-  * [[ez>community/fpga|ask questions about the FPGA reference design]]+{{page>ez_common}}
resources/fpga/xilinx/interposer/ad5669.1329732240.txt.gz · Last modified: 20 Feb 2012 11:04 by Andrei Cozma

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