This document presents the steps to setup an environment for using the EVAL-AD5570SDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5570SDZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-AD5570SDZ Evaluation Board.
The AD5570 is a single 16-bit serial input, voltage output DAC that operates from supply voltages of ±11.4 V up to ±16.5 V. Integral linearity (INL) and differential nonlinearity (DNL) are accurate to 1 LSB. During power-up, when the supply voltages are changing, VOUT is clamped to 0 V via a low impedance path.
The EVAL-AD5570 evaluation board is designed to help customers quickly prototype new AD5570 circuits and reduce design time.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
To power on the EVAL-AD5570 evaluation board, you need to provide external +12V VDD and -12V VSS supply voltage to J5 connector on the board. For more information see: EVAL-AD5570SDZ evaluation board user guide).
The following commands were implemented in this version of EVAL-AD5570 reference project for Xilinx KC705 FPGA board.
|help?||Displays all available commands.|
|register=|| Loads the DAC input register with a given value. Accepted values:
0 .. 65535 - value to be written into the register.
|ldacPin=|| Sets the output value of LDAC pin. Accepted values:
0 - sets LDAC pin low. (default)
1 - sets LDAC pin high.
|ldacPin?||Displays the value of LDAC pin.|
|clrPin=|| Sets the output value of CLR pin. Accepted values:
0 - sets CLR pin low.
1 - sets CLR pin high. (default)
|clrPin?||Displays the value of CLR pin.|
|pdPin=|| Sets the output value of PD pin. Accepted values:
0 - sets PD pin low.
1 - sets PD pin high. (default)
|pdPin?||Displays the value of PD pin.|
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design: