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resources:fpga:xilinx:interposer:ad5542a [28 Sep 2012 11:14] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina | resources:fpga:xilinx:interposer:ad5542a [09 Jan 2021 00:48] (current) – user interwiki links Robin Getz | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
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* [[adi> | * [[adi> | ||
* {{: | * {{: | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
- | * [[http:// | + | |
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Hardware ===== | ===== Required Hardware ===== | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
* FMC-SDP adapter board | * FMC-SDP adapter board | ||
* **EVAL-AD5542A** evaluation board | * **EVAL-AD5542A** evaluation board | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD5542A reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
+ | <WRAP round download 80%> | ||
+ | \\ | ||
+ | * **AD5542A Driver:** https:// | ||
+ | * **AD5542A Commands:** https:// | ||
+ | * **Xilinx Boards Common Drivers:** https:// | ||
+ | * **EDK KC705 Reference project:** https:// | ||
+ | \\ | ||
+ | </ | ||
- | * {{: | ||
- | The following table presents a short description the reference design archive contents. | + | ===== Hardware setup ===== |
- | ^ **Folder** ^ **Description** ^ | + | <WRAP round important 80%> |
- | | Bit | Contains | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore | + | Before connecting |
- | | Software | Contains the source files of the software project that will be run by the Microblaze processor.| | + | </ |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe | + | |
- | ====== Run the Demonstration Project ====== | + | * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. |
+ | * Connect the JTAG and UART cables to the KC705 and power up the FPGA board. | ||
- | {{page>ucprobe_common}} | + | <WRAP round important 80%> |
+ | \\ | ||
+ | To power on the EVAL-AD5542A evaluation board, you need to provide external +5V and -5V supply voltage to J1 connector on the board (LK8 position=B, LK9 position=A, LK7 position=A, LK3 position=B, LK2 position=A). | ||
+ | </WRAP> | ||
- | ===== Demonstration | + | ===== Reference |
+ | The following commands were implemented in this version of EVAL-AD5542A reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **register=** | Writes to the DAC register. Accepted values:\\ 0 .. 65535 - the value written to the DAC. | | ||
+ | | **register? | ||
+ | | **voltage=** | Sets the DAC output voltage. Accepted values:\\ -2500 .. +2500 - desired output voltage in milivolts. | | ||
+ | | **voltage? | ||
+ | | **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. | | ||
+ | | **ldacPin? | ||
+ | | **clrPin=** | Sets the output value of CLR pin. Accepted values:\\ 0 - sets CLR pin low.\\ 1 - sets CLR pin high.(default) | | ||
+ | | **clrPin?** | Displays the value of CLR pin. | | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5542ASDZ** evaluation board. | ||
- | {{ : | + | Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. |
- | * The communication with the board is activated / deactivated by toggling the **// | + | The following image shows a generic list of commands in a serial |
- | * The **//DAC//** switch is used to enable/ | + | {{ : |
- | * The **// | + | |
- | * The **//CLR//** switch is used to control the Asynchronous Clear Input of the AD5542A. When the CLR switch is active all LDAC pulses are ignored. When the CLR switch is deactivated the DAC register is cleared to the model selectable midscale. | + | |
- | * The **//DAC Value//** slider is used to set the value to be loaded into the DAC register. The selected value is displayed in the numeric box next to the slider. | + | |
- | ===== Troubleshooting ===== | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | ===== Software Project Setup ===== |
- | * Check that the evaluation board is powered as instructed in the board' | + | {{page> |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
* [[resources: | * [[resources: | ||
{{page> | {{page> |