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resources:fpga:xilinx:interposer:ad5421 [20 Feb 2012 14:24] – created Adrian Costinaresources:fpga:xilinx:interposer:ad5421 [09 Jan 2021 00:48] (current) – user interwiki links Robin Getz
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>AD5421|EVAL-AD5421SDZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5421SDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>AD5421|EVAL-AD5421SDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit. Below is presented a picture of the EVAL-AD5421SDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :resources:fpga:xilinx:interposer:img_ad5421.jpg }} {{ :resources:fpga:xilinx:interposer:img_ad5421.jpg }}
  
-For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: +{{page>common_sdp}}
-  * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)** +
-  * a compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]] +
-  * corresponding PC software +
-The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software.  Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.+
  
 Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5421SDZ** Evaluation Board. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5421SDZ** Evaluation Board.
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   * [[adi>AD5421|AD5421 Product Info]] - pricing, samples, datasheet   * [[adi>AD5421|AD5421 Product Info]] - pricing, samples, datasheet
   * [[adi>/static/imported-files/user_guides/UG-250.pdf|EVAL-AD5421SDZ evaluation board user guide]]   * [[adi>/static/imported-files/user_guides/UG-250.pdf|EVAL-AD5421SDZ evaluation board user guide]]
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] +  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]]+
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Hardware ===== ===== Required Hardware =====
  
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
   * FMC-SDP adapter board   * FMC-SDP adapter board
   * **EVAL-AD5421** evaluation board   * **EVAL-AD5421** evaluation board
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.6. 
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200. 
 +  * The EVAL-AD5421 reference project for Xilinx KC705 FPGA.
  
 ===== Downloads ===== ===== Downloads =====
- +<WRAP round download 80%> 
-  * {{:resources:fpga:xilinx:interposer:ad5421_evalboard.zip|Reference Design Files}} +\\ 
- +  * **AD5421 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/drivers/dac/ad5421 
-The following table presents a short description the reference design archive contents. +  * **AD5421 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5421 
- +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common 
-^ **Folder** ^ **Description** ^ +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +</WRAP>
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | +
 ====== Run the Demonstration Project ====== ====== Run the Demonstration Project ======
  
-{{page>ucprobe_common}}+===== Hardware setup =====
  
-===== Demonstration Project User Interface =====+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5421SDZ** evaluation board.+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-{{ :resources:fpga:altera:bemicro:interface5421.png?400 }}+<WRAP round important 80%> 
 +\\ 
 +To power on the EVAL-AD5421 evaluation board, you need to provide external differential supply voltage from LOOP- to LOOP+ (for more information see: [[adi>/static/imported-files/user_guides/UG-250.pdf|EVAL-AD5421SDZ evaluation board user guide]]). 
 +</WRAP>
  
 +===== Reference Project Overview =====
 +The following commands were implemented in this version of EVAL-AD5421 reference project for Xilinx KC705 FPGA board.
 +^ Command ^ Description ^
 +| **help?** | Displays all available commands. |
 +| **reset!** | Resets the AD5421 device. |
 +| **current=** | Sets the output current. Accepted values:\\ 4 .. 20 - the desired output current in milliamps. |
 +| **current?** | Displays the output current. |
 +| **register=** | Writes to the DAC register. Accepted values:\\ 0 .. 65535 - the value written to the DAC. |
 +| **register?** | Displays the last written value to the DAC register. |
 +| **offset=** | Sets the offset. Accepted values:\\ -32768 .. +32767 - digital offset adjustment(LSBs) |
 +| **offset?** | Displays the offset. |
 +| **gain=** | Sets the gain. Accepted values:\\ -65535 .. 0 - digital gain adjustment(LSBs) |
 +| **gain?** | Displays the gain. |
 +| **temp?** | Displays the die temperature. |
 +| **vloop?** | Displays the Vloop - COM voltage. |
 +| **faultReg?** | Displays the Fault register. |
  
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. 
  
-**Section B** is used to load different values into the AD5421 registers.+Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
  
-  * A DAC Value is set by using the corresponding slider. The value set by the slider can be read on the red seven segment display next to the slider.+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }}
  
-  * An OFFSET Value is set by using the corresponding slider. The value set by the slider can be read on the red seven segment display next to the slider. 
  
-  * A GAIN Value is set by using the corresponding slider. The value set by the slider can be read on the red seven segment display next to the slider. +===== Software Project Setup ===== 
- +{{page>import_workspace}}
-**Section C** is used to read back values from the AD5421. +
- +
-Each green seven segment display is used to show one of the values read from the AD5421: +
- +
-  * DAC Value read - The value programmed in the DAC Register +
- +
-  * Digital Offset Adjustment (LSB) - See AD5421 datasheet page 28 for formula +
- +
-  * Digital Gain Adjustment at Full-Scale Output - See AD5421 datasheet page 28 for formula +
- +
-  * AD5421 Temperature - Temperature read by the AD5421 +
- +
-  * VLoop-COM Voltage - The Voltage drop between the VLoop pin and the COM pin of the AD5421 +
- +
-  * Loop Current Value - See AD5421 datasheet page 25  for formula +
- +
-  * Loop Current Value Optimized - See AD5421 datasheet page  29 for formula +
- +
-  * Fault register - Each LED turns on if a bit in the Fault register is set. See AD5421 datasheet page 27 for more details about each fault +
- +
-===== Troubleshooting ===== +
- +
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +
-  * Check that the evaluation board is powered as instructed in the board's user guide. +
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. +
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+
  
 ====== More information ====== ====== More information ======
-  * [[ez>community/fpga|ask questions about the FPGA reference design]] +  * [[resources:tools-software:linux-drivers:iio-dac:ad5421|AD5421 IIO DAC Linux Driver]] 
- +{{page>ez_common}}
resources/fpga/xilinx/interposer/ad5421.1329744263.txt.gz · Last modified: 20 Feb 2012 14:24 by Adrian Costina

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