This document presents the steps to setup an environment for using the EVAL-AD5272SDZ evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the Micrium µC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-AD5272SDZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-AD5272SDZ Evaluation Board.
The EVAL-AD5272SDZ evaluation board is a member of a growing number of boards available for the SDP. Designed to help customers evaluate performance or quickly prototype new AD5272 circuits and reduce design time, the EVAL-AD5272SDZ evaluation board can operate in single-supply and dual-supply mode and incorporates an internal power supply powered from the USB.
The AD5272 is a single-channel, 1024-position digital rheostat that combine industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. The AD5272 ensure less than 1% end-to-end resistor tolerance error and offer 50-times programmable (50-TP) memory. The guaranteed industry leading low resistor tolerance error feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. The AD5272 device wiper settings are controllable through the I2C-compatible digital interface. Unlimited adjustments are allowed before programming the resistance value into the 50-TP memory. The AD5272 does not require any external voltage supply to facilitate fuse blow and there are 50 opportunities for permanent programming. During 50-TP activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer).
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
The following table presents a short description the reference design archive contents.
|Bit||Contains the KC705 configuration file that can be used to program the system for quick evaluation.|
|Microblaze||Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA.|
|Software||Contains the source files of the software project that will be run by the Microblaze processor.|
|uCProbeInterface||Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory.|
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
At this point everything is set up and it is possible to start the evaluation of the ADI hardware through the controls in the uC-Probe application provided in the reference design.
Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.
Select uC-Probe options.
Set target board communication protocol as RS-232
Setup RS-232 communication settings
The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-AD5272SDZ evaluation board.
Section A is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board. See the Troubleshooting section for indications on how to fix the communication problems.
Section B displays the data that is read from the RDAC register.
Section C is used to write data to RDAC register.
Section D allows access to the control register, enabling or disabling the resistor performance mode, RDAC write protection, and the 50-TP memory.
Section E is used to reset and to shutdown the device.
Section F is used read/write the 50-TP memory.
In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: