This document presents the steps to setup an environment for using the EVAL-AD5110SDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5110SDZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-AD5110SDZ Evaluation Board.
The EVAL-AD5110SDZ evaluation board is a member of a growing number of boards available for the SDP. Designed to help customers evaluate performance or quickly prototype new AD5110 circuits and reduce design time, the EVAL-AD5110SDZ evaluation board can operate in single-supply and incorporates an internal power supply powered from the USB.
The AD5110 provides a nonvolatile solution for 128-/64-/32-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W pins. The low resistor tolerance, low nominal temperature coefficient and high bandwidth simplify open-loop applications, as well as tolerance matching applications. The new low wiper resistance feature minimizes the wiper resistance in the extremes of the resistor array to only 45 Ω, typical. The wiper settings are controllable through an I2C-compatible digital interface that is also used to readback the wiper register and EEPROM content. Resistor tolerance is stored within EEPROM, providing an end-to-end tolerance accuracy of 0.1%.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
The following commands were implemented in this version of EVAL-AD5110 reference project for Xilinx KC705 FPGA board.
|help?||Displays all available commands.|
|reset!||Makes a software reset of the device.|
|rdac=|| Writes to the RDAC register. Accepted values:
0 .. 127 - the value written to RDAC.
|rdac?||Displays the last written value in RDAC register.|
|rdacToEeprom!||Writes the content of RDAC register to EEPROM.|
|wiper?||Displays the wiper resistance from EEPROM.|
|tolerance?||Displays the resistance tolerance from EEPROM.|
|power=|| Turns on/off the device. Accepted values:
0 - turns off the device.
1 - turns on the device.
|power?||Displays the power status of the device.|
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design: