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resources:fpga:xilinx:fmc:ad9739a [03 Apr 2014 15:50] – [Downloads] Charly El-Khoury | resources:fpga:xilinx:fmc:ad9739a [03 Apr 2014 17:41] – adding revC Charly El-Khoury | ||
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+ | ====== AD9739A Native FMC Card / Xilinx Reference Designs ====== | ||
+ | |||
+ | ===== Introduction ===== | ||
+ | The [[adi> | ||
+ | |||
+ | ===== Supported Devices ===== | ||
+ | |||
+ | * [[adi> | ||
+ | |||
+ | {{: | ||
+ | |||
+ | <WRAP round 80% alert> | ||
+ | * does not meet the mechanical form factor (too tall, too long), | ||
+ | * does not include the I2C EEPROM as specified in Rule 5.69, | ||
+ | * Also see " | ||
+ | It was designed, and meets the needs of prototyping platforms, and will work with FPGA Development systems which include an FMC connector. It may not mechanically fit on other ANSI/VITA 57.1 carrier cards.</ | ||
+ | |||
+ | ===== Supported Carriers ===== | ||
+ | |||
+ | * [[xilinx> | ||
+ | * [[xilinx> | ||
+ | * [[xilinx> | ||
+ | * [[xilinx> | ||
+ | ===== Quick Start Guide ===== | ||
+ | |||
+ | The reference design has been tested on ML605(Virtex-6), | ||
+ | |||
+ | {{analogTV> | ||
+ | ==== Required Hardware ==== | ||
+ | * ML605/ | ||
+ | * AD9739A-FMC-EBZ board | ||
+ | * Spectrum Analyzer | ||
+ | |||
+ | |||
+ | ==== Required Software ==== | ||
+ | * Xilinx ISE Design Suite 14.4 | ||
+ | * A UART terminal (Tera Term/ | ||
+ | * [[http:// | ||
+ | |||
+ | ==== Running Demo (SDK) Program ==== | ||
+ | |||
+ | To begin, connect the AD9739A-FMC-EBZ board to the FMC-LPC connector of ML605 board (see image below). If using KC705 use FMC-LPC, if using VC707 use FMC1-HPC. Connect power and two USB cables from the PC to the //JTAG// and //UART// USB connectors on the edge of the ML605. A spectrum analyzer should be connected to the output SMA jack (OUT/J1). This quick start program uses a 2.5GHz DAC clock and generates a 300MHz tone. Adjust your spectrum analyzer accordingly. On the AD9739A-FMC board, ensure that the SPI source jumper (SPI SRC/P2) is set to FMC and the clock source jumper (CLOCK SOURCE/S1) is set to ADF4350 position. The USB connection on the AD9739A-FMC-EBZ and the SMA Clock Input (SMA CLKIN/J3) are not used in this example. After the hardware setup, turn the power on to the ML605. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | Run the **// | ||
+ | |||
+ | **Note:** The // | ||
+ | |||
+ | If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9739A and ADF4350, you have to tell the program from where it should take the input data(from DMA or DDS). Then the program continuously monitors the MU Controller and LVDS Receiver lock status. If either of them are out of lock, the program quits itself with an error. You may also quit the program by pressing [q] key. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | The specturm analyzer output is shown below. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | ==== DOCSIS Results ==== | ||
+ | |||
+ | [[wp> | ||
+ | |||
+ | Adjacent Channel Leakage Ratio (ACLR) is the ratio of the reconstructed signal power to the power measured in an adjacent channel measured in dB. This is critical in many applications, | ||
+ | |||
+ | Click on any picture, to make it bigger, and see the measurement results. | ||
+ | |||
+ | === Single Channel === | ||
+ | {{: | ||
+ | {{: | ||
+ | |||
+ | |||
+ | |||
+ | === Four Channel === | ||
+ | {{: | ||
+ | {{: | ||
+ | |||
+ | |||
+ | === Eight Channel === | ||
+ | {{: | ||
+ | {{: | ||
+ | |||
+ | |||
+ | ===== Using the reference design ===== | ||
+ | |||
+ | ==== Functional description ==== | ||
+ | |||
+ | The reference design consists of two functional modules, a DDS/LVDS interface and a SPI interface. It is part of an AXI based microblaze system as shown in the block diagram below. It is designed to support linux running on microblaze. All other peripherals are available from Xilinx as IP cores. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | |||
+ | The DDS consists of a Xilinx DDS IP core and a DDR based data generator. The core generates 6 samples at every fDAC/3 clock cycles for each port of AD9739A. | ||
+ | |||
+ | The SPI interface allows programming the ADF4350 and/or AD9739A. The provided SDK software shows the initial setup required for both the devices for a 2.5GHz DAC clock with a 300MHz single tone DDS. | ||
+ | |||
+ | |||
+ | ==== Registers ==== | ||
+ | |||
+ | Please see the regmap.txt file in the pcores directory. | ||
+ | |||
+ | |||
+ | ===== Hardware Reference ===== | ||
+ | There are several hardware options available on the AD9739A-FMC-EBZ: | ||
+ | |||
+ | ==== Clock Selection ==== | ||
+ | Two clock paths are available to drive the clock input on the AD9739A-FMC-EBZ. The factory default option connects the [[adi> | ||
+ | |||
+ | Alternatively, | ||
+ | |||
+ | ==== SPI Source Selection ==== | ||
+ | There are two options for driving the SPI port of the [[adi> | ||
+ | |||
+ | The first, which is used in the quick start guide above, is to have all the SPI lines driven by the FPGA, lines which are connected to FMC connector. In this case, jumper SPI SRC (P2) is set to FMC. A level translator ([[adi> | ||
+ | |||
+ | The other option for driving the SPI is to use the on-board USB microcontroller. In this case, jumper SPI SRC (P2) is set to USB. Now the data path is still connected to the FMC connector, but the SPI lines are driven by the microcontroller. This allows the use of the graphical interface PC software that is included with the standard Analog Devices evaluation boards(DAC Software Suite). This option makes it easier to experiment with various settings on the parts before programming the parts from the FPGA. | ||
+ | |||
+ | <WRAP round 80% tip> | ||
+ | \\ | ||
+ | For the highest performance (noise floor below -105dBm), do not power the USB microcontroller while taking measurements. After configuring the part over USB, remove jumper P2. This does not apply to the FMC SPI option, in which case the USB microcontroller is already powered down | ||
+ | \\ | ||
+ | </ | ||
+ | |||
+ | ===== Using the Software Reference Design ===== | ||
+ | |||
+ | The Software Reference Design contains an example on how to: | ||
+ | * Initialize the AD9739A evaluation board | ||
+ | * Initialize the AD9739A HDL core | ||
+ | * Generate a 300MHz single tone DDS | ||
+ | |||
+ | The software project contains 3 components: the AD9739A-FMC-EBZ reference design files, the AD9739A driver and the ADF4350 driver. All the components have to be downloaded from the links provided in the **Downloads** section. | ||
+ | ==== AD9739A Software Driver ==== | ||
+ | |||
+ | Below is presented a short description of all the functions provided in the driver. | ||
+ | |||
+ | |||
+ | |< 100% 40% 60% >| | ||
+ | ^ Function | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | float **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | |||
+ | ==== Software Setup ==== | ||
+ | |||
+ | The **HDL Reference Design** for each supported Xilinx FPGA board contains a folder called // | ||
+ | These are the steps that need to be followed to recreate the software project: | ||
+ | * Copy the // | ||
+ | * Copy the no-OS drivers source code to the // | ||
+ | {{: | ||
+ | * Open the Xilinx SDK. When the SDK starts it asks you to provide a folder where to store the workspace. Any folder can be provided. | ||
+ | * In the SDK select the // | ||
+ | {{: | ||
+ | * In the //Import// window select the // | ||
+ | {{: | ||
+ | * In the //Import Projects// window select the // | ||
+ | {{: | ||
+ | * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the // | ||
+ | {{: | ||
+ | * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. | ||
+ | |||
+ | The example code is located in the ”// | ||
+ | |||
+ | ===== Using the ADF4350 USB SPI Software ===== | ||
+ | |||
+ | After installing the graphical interface PC software that is included with the standard Analog Devices evaluation boards(DAC Software Suite), you can find the software controlling ADF4350 clock chip at Start > Programs > Analog Devices > AD9739A > ADF4350 SPI for AD9739A-FMC-EBZ. Once opened, select File…Open Setup File. Browse for the file 2_5GHz for AD9739A.ini, | ||
+ | |||
+ | {{section> | ||
+ | |||
+ | ===== Downloads ===== | ||
+ | |||
+ | The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.\\ | ||
+ | \\ | ||
+ | <WRAP round important 80%> | ||
+ | \\ | ||
+ | The software project contains 3 components: the AD9739A-FMC-EBZ reference design files, the AD9739A driver and the ADF4350 driver. All the components have to be downloaded from the links below. | ||
+ | </ | ||
+ | |||
+ | **HDL Reference Designs:** | ||
+ | |||
+ | <WRAP round download 80%> | ||
+ | * **ML605 HDL Reference Design: ** {{: | ||
+ | * **KC705 HDL Reference Design: ** {{: | ||
+ | * **VC707 HDL Reference Design: ** {{: | ||
+ | * **AC701 HDL Reference Design: ** {{: | ||
+ | </ | ||
+ | |||
+ | **no-OS Software:** | ||
+ | <WRAP round download 80%> | ||
+ | * **AD9739A Driver: | ||
+ | * **ADF4350 Driver: | ||
+ | * **AD9739A-FMC-EBZ Reference Design: ** https:// | ||
+ | </ | ||
+ | |||
+ | **Board Files:** | ||
+ | |||
+ | <WRAP round download 80%> | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * [[resources: | ||
+ | </ | ||
+ | |||
+ | <WRAP round alert 80%> | ||
+ | Rev A and Rev B of this board mistakenly do not follow Rule 5.62 on the ANSI/VITA 57.1 spec - //"The FMC module shall connect TDI to TDO, if the module does not use the JTAG interface."// | ||
+ | </ | ||
+ | |||
+ | <WRAP round help 80%> | ||
+ | \\ | ||
+ | * Questions? [[http:// | ||
+ | \\ | ||
+ | </ | ||
+ | |||
+ | ==== Reference Design Contents ==== | ||
+ | |||
+ | ^ HDL Reference Design | ||
+ | | license.txt | ADI license & copyright information. | | ||
+ | | system.mhs | MHS file. | | ||
+ | | system.xmp | XMP file (use this file to build the reference design). | | ||
+ | | data/ | UCF file and/or DDR MIG project files. | | ||
+ | | docs/ | Documentation files (Please note that this wiki page is the documentation for the reference design). | | ||
+ | | sw/ | Software (Xilinx SDK) & bit file(s). | | ||
+ | | cf_lib/ | ||
+ | ^ Software Reference Design | ||
+ | | cf_ad9739a.h | Header file containing the registers definitions for the AD9739A HDL core. | | ||
+ | | cf_ad9739a.c | Implementation of the AD9739A HDL core access functions and ADC test and capture functions. | | ||
+ | | spi.h | Header file for the Xilinx AXI SPI driver. | | ||
+ | | spi.c | Implementation file for the Xilinx AXI SPI driver. | | ||
+ | | main.c | Implementation of the program' | ||
+ | ^ AD9739A Software Driver | ||
+ | | AD9739a.h | AD9739A software driver header file. | | ||
+ | | AD9517_cfg.h | AD9739A software driver configuration file. | | ||
+ | | AD9517.c | AD9739A software driver implementation file. | | ||
+ | ^ ADF4350 Software Driver | ||
+ | | ADF4350.h | ADF4350 software driver header file. | | ||
+ | | ADF4350_cfg.h | ADF4350 software driver configuration file. | | ||
+ | | ADF4350.c | ADF4350 software driver implementation file. | | ||
+ | |||
+ | ==== Third Party Bitstreams ==== | ||
+ | |||
+ | {{page>/ | ||
+ | |||
+ | * [[http:// | ||
+ | * [[http:// | ||
+ | * [[http:// | ||
+ | * [[http:// | ||
+ | |||
+ | ===== More information ===== | ||
+ | <WRAP round help 80%> | ||
+ | |||
+ | * [[http:// | ||
+ | * [[http:// | ||
+ | * [[ez> | ||
+ | * [[ez> | ||
+ | </ |