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resources:fpga:xilinx:fmc:ad9467 [04 Jun 2018 14:45] – Updated build and release instructions. Pointing to 2018_r1 release as the latest release Adrian Costina | resources:fpga:xilinx:fmc:ad9467 [19 Apr 2024 11:59] (current) – Add reference to AD9467/Zed using ACE iulia Moldovan | ||
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===== Introduction ===== | ===== Introduction ===== | ||
- | The [[adi> | + | The [[adi> |
- | ===== Evaluation Board Hardware ===== | ||
- | To find out more information about the [[http:// | + | ===== Supported devices ===== |
- | {{: | + | * [[adi> |
- | ==== Clock Selection ==== | ||
- | The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467. | + | ===== Supported carriers ===== |
- | The **default clock input** circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input (J201) is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. | + | |
+ | | ||
- | The evaluation board can be set up to be clocked from the **crystal oscillator**, | + | ===== Block design ===== |
- | A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[http://www.analog.com/ | + | ==== Xilinx block diagram ==== |
+ | {{:resources: | ||
- | <WRAP round important 100%> | + | ==== AD9467 FMC card block diagram ==== |
- | \\ | + | {{:resources:fpga:xilinx:fmc: |
- | Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path. The schematic of the board can be found at the [[http:// | + | |
- | </ | + | |
- | ===== Supported Carriers ===== | ||
- | * [[xilinx> | + | ==== Description ==== |
- | * [[http:// | + | |
- | ==== Other Required Hardware ==== | + | The reference design is built on a ARM/ |
- | * Signal synthesizer (for data and/or clock input). | + | Through an SPI interface, the software can access the AD9467/ |
- | ==== Required Software ==== | + | The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. |
- | * We're upgrade the Xilinx tools on every release. The supported version number can be found in our HDL [[https:// | ||
- | * A UART terminal (Tera Term/ | ||
- | ===== Using the HDL reference design ===== | + | ==== Clock selection |
- | <WRAP round info 100%> | + | The board provides three (some modification maybe necessary) possible clock paths for clocking the AD9467, as follows: |
- | Instruction about how to build the HDL design | + | |
+ | === Default clock input === | ||
+ | |||
+ | The **default clock input** circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter | ||
+ | |||
+ | === Crystal oscillator === | ||
+ | |||
+ | The evaluation board can be set up to be clocked from the **crystal oscillator**, | ||
+ | * Install C205 and C206 | ||
+ | * Remove C202 | ||
+ | Jumper P200 is used to disable the oscillator from running. \\ | ||
+ | |||
+ | === Clock generator AD9517 === | ||
+ | |||
+ | A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[adi> | ||
+ | * Populate (C304, C305) for LVPECL clock driver **or** (C306, C307) for LVDS clock driver, with 0.1 µF capacitors | ||
+ | * Remove C209 and C210 to disconnect the default clock path inputs | ||
+ | |||
+ | The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options.\\ | ||
+ | |||
+ | <WRAP round important 100%> | ||
+ | Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path. The schematic of the board can be found {{ :resources:fpga: | ||
</ | </ | ||
- | ==== Functional description ==== | ||
- | The reference design is built on a ARM/ | + | ==== Hardware description ==== |
- | {{:resources:fpga:xilinx:fmc: | + | To find out more information about the [[adi> |
- | Through an SPI interface, the software can access the AD9467/ | + | {{: |
- | The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. | ||
- | ==== Good To Know ==== | + | ===== Quick start guide ===== |
+ | |||
+ | ==== Required hardware ==== | ||
+ | |||
+ | * [[https:// | ||
+ | * [[adi> | ||
+ | * Signal/ | ||
+ | * Signal generator (analog input, for data capture) | ||
+ | * Signal synthesizer (for data and/or clock input). | ||
+ | |||
+ | ==== Required software ==== | ||
+ | |||
+ | * We're upgrading the Xilinx tools on every release. The supported version number can be found in our HDL [[/ | ||
+ | * A UART terminal (Tera Term/ | ||
+ | |||
+ | ===== Using the HDL reference design ===== | ||
+ | |||
+ | Check this wiki page if you're not familiar about [[: | ||
The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the msb is inverted. | The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the msb is inverted. | ||
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* Capture data from the AD9467 using DMA transfers | * Capture data from the AD9467 using DMA transfers | ||
- | The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the [[http:// | + | The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the [[/ |
==== AD9467 Software Driver ==== | ==== AD9467 Software Driver ==== | ||
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<WRAP round info 100%> | <WRAP round info 100%> | ||
- | Instruction about how to create a software application can be found [[http:// | + | Instruction about how to create a software application can be found [[/ |
</ | </ | ||
- | The exact location of the no-OS source files can be found in the [[http:// | + | <note important> |
- | + | ||
- | ===== Downloads ===== | + | |
- | + | ||
- | The HDL Reference Designs | + | |
- | + | ||
- | **HDL Reference Designs: | + | |
- | + | ||
- | <WRAP round download> | + | |
- | **latest release** | + | |
- | * **ZED HDL Reference Design: ** https:// | + | |
- | * **KC705 HDL Reference Design: ** https:// | + | |
- | </ | + | |
- | + | ||
- | **no-OS Software: | + | |
- | <WRAP round download> | + | |
- | **latest release** | + | |
- | * **AD9467 Driver: | + | |
- | * **AD9517 Driver: | + | |
- | * **AD9467-FMC-EBZ Reference Design: ** https:// | + | |
- | </WRAP> | + | |
**Board Files:** | **Board Files:** | ||
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* {{: | * {{: | ||
* {{: | * {{: | ||
- | * {{: | + | * {{ : |
- | **Note:** C302 and C303 are not installed as indicated in the Schematic and BOM. | + | |
</ | </ | ||
+ | |||
+ | |||
+ | ===== Resources ===== | ||
+ | |||
+ | * [[repo> | ||
+ | * [[: | ||
+ | * [[adi> | ||
+ | * {{: | ||
+ | * [[repo> | ||
+ | * [[repo> | ||
+ | * [[repo> | ||
+ | * [[https:// | ||
+ | * [[https:// | ||
+ | * [[https:// | ||
+ | |||
+ | |||
===== More information ===== | ===== More information ===== | ||
- | <WRAP round help 80%> | + | * [[: |
- | \\ | + | * [[: |
- | [[ez> | + | * [[: |
- | </ | + | * [[: |
+ | * [[: | ||
+ | * [[: | ||
+ | |||
+ | |||
+ | ===== Support ===== | ||
+ | |||
+ | Analog Devices will provide **limited** online support for anyone using the reference design with Analog Devices components via the [[ez> | ||
+ | |||
+ | It should be noted, that the older the tools' versions and release branches are, the lower the chances to receive support from ADI engineers. |