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resources:fpga:xilinx:fmc:ad9467 [12 Mar 2014 18:05] – [AD9467 Native FMC Card / Xilinx Reference Design] Cybel Ranresources:fpga:xilinx:fmc:ad9467 [10 Apr 2014 10:50] – [Clock Selection] Istvan Csomortani
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 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
-To begin, connect the AD9467-FMC-EBZ board to the FMC-LPC connector of ML605 (see image below) or KC705 or Zed board. If using VC707 connect to the FMC1-HPC. Connect power and two USB cables from the PC to the //JTAG// and //UART// USB connectors on the edge of the ML605. **The demo program uses the on board AD9517-4 to generate the  input clock for the AD9467 A/D converter. ** The provided SDK application initialize the AD9517's third channel to 250 Mhz. Connect a signal source to the J100 SMA connector of the FMC card, it is recommended to use filter to filter out the possible high frequencies of the input signal, in this way to ensure the quality of the conversion. After the hardware setup, turn the power on to the ML605.+To begin, connect the AD9467-FMC-EBZ board to the FMC-LPC connector of ML605 (see image below) or KC705 or Zed board. If using VC707 connect to the FMC1-HPC. Connect power and two USB cables from the PC to the //JTAG// and //UART// USB connectors on the edge of the ML605. ** The demo program uses the default board configuration that uses an external clock (AD9517 is powered down). ** However, since AD9517 is still access-able via SPI, the SDK program configures it for a pass through mode. Connect a clock source to the CLKIN SMA connector and a signal source to the AIN SMA connector of the FMC card. After the hardware setup, turn the power on to the ML605.
  
 {{:resources:fpga:xilinx:fmc:cf_ad9467_setup.jpg?200|Hardware setup}} {{:resources:fpga:xilinx:fmc:cf_ad9467_setup.jpg?200|Hardware setup}}
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 The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467.  The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467. 
  
-  * Active clock path or using the AD9517(default) : You may use either the PECL (OUT3) or the LVDS (OUT5) outputs. The optional oscillator may be used as a clock source for the AD9517 REF or CLK inputs+  * External passive clock (default): A SMA connector is provided for an external clock source. 
-  * Optional external passive clock: A SMA connector is provided for an external clock source.+  * Optional active clock path or using the AD9517 : You may use either the PECL (OUT3) or the LVDS (OUT5) outputs. The optional oscillator may be used as a clock source for the AD9517 REF or CLK inputs.
   * Optional oscillator: The connector P200 must be set to OSC-ON position. This can be enabled through the passive or active (AD9517) path.   * Optional oscillator: The connector P200 must be set to OSC-ON position. This can be enabled through the passive or active (AD9517) path.
  
resources/fpga/xilinx/fmc/ad9467.txt · Last modified: 06 Nov 2023 14:23 by iulia Moldovan