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This version (26 Jul 2013 20:53) was approved by rejeesh.The Previously approved version (11 Feb 2013 20:19) is available.Diff

AD9265 Native FMC Card / ML605 Xilinx Reference Design

Introduction

The AD9265 is a 16-bit, 125MSPS analog-to-digital converter (ADC) featuring a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring it's internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC.

Supported Devices

  • AD9265-FMC

Supported Carriers

Quick Start Guide

The reference design has been tested with ML605. It should be easily portable to other boards such as KC705 and VC707, only UCF and MHS files need to be changed. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). This bit file configuration also captures the test mode outputs of ADC.

Required Hardware

  • ML605 board
  • AD9265-FMC board
  • Signal generator (for clock)
  • Signal generator (for data)

Required Software

  • Xilinx ISE (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). Use the latest version or the one used in the reference design.
  • A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
  • Xilinx Chipscope Analyzer (for signal capture plot).

Running Demo (SDK) Program

To begin, connect the AD9265-FMC board to the FMC-LPC connector of ML605 board (see image below). Connect power and two USB cables from the PC to the JTAG and UART USB connectors on the edge of the ML605. The demo program uses the default board configuration that uses an external clock (AD9517 is powered down). However, since AD9517 is still access-able via SPI, the SDK program configures it for a pass through mode. Connect a 125MHz clock source to the CLKIN SMA (J201) connector and a signal source to the AIN SMA (J100) connector of the FMC card. After the hardware setup, turn the power on to the ML605.

Hardware setup

Start IMPACT, and initialze the JTAG chain. The program should recognize the Virtex 6 device. Start a UART terminal (set to 57600 baud rate) and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9265 and AD9517, the program enables different test patterns available on the ADC.

Terminal

After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available on pins [15:0] of the chipscope signal.

Chipscope Busplot

Using the reference design

Functional description

The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.

Functional Block Diagram

It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.

Registers

Refer to the regmap.txt file inside the pcores directory.

Clock Selection

The board provides three (some modification maybe necessary) possible clock path for clocking the AD9265.

  • External passive clock (default).
  • Optional active clock path using the AD9517.
  • Optional oscillator.

Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path.

Downloads

Board Files:

FPGA Referece Designs:

Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See generating Xilinx netlist/verilog files from xco files for details.

Tar file contents

The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.

license.txt ADI license & copyright information.
system.mhs MHS file.
system.xmp XMP file (use this file to build the reference design).
data/ UCF file and/or DDR MIG project files.
docs/ Documentation files (Please note that this wiki page is the documentation for the reference design).
sw/ Software (Xilinx SDK) & bit file(s).
../cf_lib/edk/pcores/* The pcores directory.

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