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resources:fpga:xilinx:fmc:ad-fmcomms1-ebz [08 Jun 2012 16:24]
rejeesh [Running Demo (SDK) Program] 		resources:fpga:xilinx:fmc:ad-fmcomms1-ebz [04 Apr 2013 18:19] (current)
rejeesh [Download]
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-====== AD-FMCOMMS1-EBZ Reference Design ====== +====== AD-FMCOMMS1-EBZ HDL Reference Design ======
-  +
-<WRAP alert>This information is **preliminary**. This page contains material that is subject to change without notice.+
  
-Status: +===== Supported Devices =====
-  * both Tx and Rx are functional, and hits design goals +
-  * clock sync (MIMO 2x2) is functional, and hits design goals +
-  * Some issues that track carrier board (noise floor) - needs to be resolved before final release to manufacture. +
-</WRAP>+
  
-===== Introduction =====+  * [[adi>AD-FMCOMMS1-EBZ]]
  
-The FMCCOMMS1-EBZ high-speed analog module is designed to showcase the latest generation high-speed data converters.  The FMCCOMMS1-EBZ provides the analog front-end for a wide range of compute-intensive FPGA-based radio applications. +===== Supported Carriers =====
  
-The AD-FMCOMMS1-EBZ is an analog front end hardware platform that addresses a broad range of research, academic, industrial and defense applications. The AD-FMCOMMS1-EBZ enables RF applications from 400MHz to 4 GHz. The module is customizable to a wide range of frequencies by software without any hardware changes, providing options for GPS or IEEE 1588 Synchronization, and MIMO configurations.+  * [[xilinx> ML605]]  
 +  * [[xilinx> KC705]]  
 +  * [[xilinx> VC707]]  
 +  * [[xilinx> ZC702]]  
 +  * [[xilinx> ZC706]]  
 +  * [[http://www.zedboard.org| Zed Board]] 
  
-When combined with the Xilinx ZYNQ® Software-Defined Radio Kit, FMCCOMMS1-EBZ enables a variety of wireless communications functions at the physical layer, from baseband to RF. With up to 4 GB of flash storage space, 512 MB of RAM, Gigabit Ethernet interface (depending on the base platform) and a Linux image built specifically for the AD-FMCOMMS1-EBZ, you can get everything you need for a easy out of the box experience.  The platform offers enough flexibility for many applications, and supports streaming data, and standard web interfaces to analyze transmited RF data.+===== Download ======
  
-{{  :resources:fpga:xilinx:fmc:dscn1188.png?direct&400  |FMComms + Zynq Board}}+FPGA Reference Designs on GitHub :
  
-==== Specifications &amp; Features ====+&lt;WRAP round download 80%> 
 +  * https://github.com/analogdevicesinc/fpgahdl_xilinx/archive/ad_fmcomms1_ebz_edk_14_4_2013_04_04.tar.gz 
 +  * https://github.com/analogdevicesinc/fpgahdl_xilinx/archive/ad_fmcomms1_ebz_edk_14_4_2013_04_04.zip 
 +  * https://github.com/analogdevicesinc/fpgahdl_xilinx.git 
 +  * https://github.com/analogdevicesinc/fpgahdl_xilinx/tags 
 +</WRAP>;
  
-  * General purpose design suitable for any application +<WRAP round help 80%> 
-  * Software tunable across wide frequency range (400MHz to 4GHz) with 125MHz channel bandwidth (250MSPS ADC, 1GSPS DAC) +  * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&amp;container=2061|Ask Help &amp; Support]]. 
-  * RF section bypass for baseband sampling +</WRAP>
-  * Phase and frequency synchronization on both transmit and receive paths +
-  * Allows high channel density +
-  * LPC FMC Compatible, meets VITA specifications except card length +
-  * Powered from single FMC connector +
-  * Supports MIMO radio, with less than 1 sample sync on both ADC and DAC +
-  * Includes schematics, layout, BOM, HDL, Linux drivers and application software  +
-  * Supports add on cards for spectrum specific designs (PA, LNA etc) +
-  * Common I&lt;sup&gt;2</sup>C access for all device registers+
  
-==== Applications ====+===== Generating Xilinx netlist files ======
  
-  * Wireless communications demonstration and learning tool +The repository will not contain Xilinx netlist files. If you need to build the design, you must generate these files. The following steps illustrate the process using coregen.
-  * Remote radio head +
-  * Software-defined radio +
-  * Satellite modems +
-  * Test and measurement equipment +
-  * Radar and advanced imaging  +
-  * General purpose data acquisition+
  
-==== Functional description ==== 
  
-A functional block diagram of the system is given below. The system consists of four functional partitions - transmit path, receive path, clocking and register access.+|Open coregen, the default path is "Xilinx Design Tools -> ISE Design Suite 14.1 -> ISE Design Tools -> 64-bit Tools -> CORE Generator"|{{:resources:fpga:xilinx:fmc:howto_coregen_1.jpg?400|}}| 
 +|If you have an existing project file, use that. Otherwise click "File->New Project" |{{:resources:fpga:xilinx:fmc:howto_coregen_2.jpg?400|}}| 
 +|Pick a directory location in this case it is "C:/fpgahdl_xilinx"|{{:resources:fpga:xilinx:fmc:howto_coregen_3.jpg?400|}}| 
 +|Under the "Part" tab, select family: "Virtex6", Device: "xc6vlx240t", package: "ff1156" and Speed Grade: "-1". This corresponds to ML605. You may use this same selection, even if you are targeting a KC705 or ZC702 board. Click on "Apply".|{{:resources:fpga:xilinx:fmc:howto_coregen_4.jpg?400|}}| 
 +|Under the "Generation" tab, select Design Entry: "Verilog". Click on "OK".|{{:resources:fpga:xilinx:fmc:howto_coregen_5.jpg?400|}}| 
 +|Now we need the list of modules to generate the netlist files. The repository contains xco files for each of the netlist file that is missing. A windows search for "*.xco" or "find" should give us the list. **find cf_lib/edk/pcores -name "*.xco"**|{{:resources:fpga:xilinx:fmc:howto_coregen_9.jpg?400|}}| 
 +|In coregen, select "Project -> Import Existing Customized IP", and add all the xco files. |{{:resources:fpga:xilinx:fmc:howto_coregen_6.jpg?400|}}| 
 +|Change the view (left bottom) to "Project IP", make sure all the xco files are imported. |{{:resources:fpga:xilinx:fmc:howto_coregen_7.jpg?400|}}| 
 +|Select "Project -> Regenerate all project IP (under current project settings)". This could take a while especially for the FFT core.|{{:resources:fpga:xilinx:fmc:howto_coregen_8.jpg?400|}}| 
 +|Once complete, copy the "*.ngc" files to the respective "netlist" and "*.v" files to the respective "hdl/verilog" directories. You may now open XPS and rebuild the project.|{{:resources:fpga:xilinx:fmc:howto_coregen_9.jpg?400|}}|
  
-{{:resources:fpga:xilinx:fmc:cf_xcomm_kc705_bd.jpg?200|Block diagram}} 
  
-==== Transmit ==== 
  
-Key components: 
-  * **[[adi>AD9122]]**, Dual, 16-Bit, 1200 MSPS, TxDAC+® Digital-to-Analog Converter with offset, phase and gain compensation. 
-  * **[[adi>ADL5375]]**, 400 MHz to 6 GHz Broadband Quadrature Modulator. 
-  * **[[adi>ADF4351]]**,  Wideband Synthesizer with Integrated VCO (35MHz to 4400MHz). 
-  * **[[adi>ADL5602]]**, 50 MHz to 4.0 GHz RF/IF Gain (20dB) Block. 
  
-In the transmit direction, the system converts complex I and Q signals to a corresponding RF signal. The [[adi>AD9122]] DAC interpolates the data and applies a frequency translation to the baseband. The complex IF shifts the fundamental signal away from DC where LO feed-through and images can be easily filtered and otherwise mitigated. This complex analog output from the DAC feeds an [[adi>ADL5375]] quadrature modulator via an appropriate filter and matching stage where it is translated to the specified RF output frequency. This signal is then passed through an image rejection filter to an [[adi>ADL5602]] for +20dB gain. The RF output power control is accomplished by adjusting the baseband data, RF outputs up to 4GHz can be synthesized in the transmit direction at power levels up to 7.5dBm.+==== Tar file contents ====
  
-The reference design generates the signals for AD9122 either from an internal DDS or external memory (via VDMA). The internal DDS consists of four independent signal generators with programmable phase offset and frequency. These four signal generators are paired to create two tones that are interleaved and driven to the DAC. +The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
- +
-==== Receive ==== +
- +
-Key components:\\ +
- +
-  * **[[adi>ADL5380]]**,  400 to 6000 MHz Quadrature Demodulator, 500MHz bandwidth. +
-  * **[[adi>AD8366]]**, DC to 600 MHz, Dual-Digital Variable Gain ( 4.5dB to 20.5dB) Amplifiers. +
-  * **[[adi>AD9643]]**, 14-Bit, 250 MSPS, Dual Analog-to-Digital Converter (ADC). +
-  * **[[adi>ADF4351]]**,  Wideband Synthesizer with Integrated VCO (35MHz to 4400MHz). +
- +
-In the receive direction, the system converts a RF signal into complex I and Q signals. The RF signal is demodulated by the [[adi>ADL5380]] to a suitable complex IF (50MHz to 200MHz). The I and Q IF signal is filtered and then passed to the AD8366 [[adi>AD8366]] DVGA, which provides upto 15.75dB of gain. An anti-alias filter is used to remove harmonics and other out of band signals before the signal is digitized with the [[adi>AD9643]]. +
- +
-The reference design transfers the received data to DDR via DMA. An optional off-line FFT core may be used to generate a spectrum plot. +
- +
-==== Clocking ==== +
- +
-Key components:\\ +
- +
-  * **[[adi>AD9548]]**, Quad/Octal Input Network Clock Generator/Synchronizer  (1Hz to 750MHz). +
-  * **[[adi>AD9523-1]]**, Low Jitter Clock Generator (1MHz to 1GHz) with 14 Outputs. +
- +
-The system may be clocked either through the on board crystal (50MHz) or from the FPGA (through FMC). The clock  +
-path mainly consists of an [[adi>AD9548]], [[adi>AD9523-1]] and two ADF4351 [[adi>ADF4351]] for the transmit and receive paths. When using multiple boards with external synchronization, the slave boards must use the clocks from the master board. +
- +
-The reference design generates the reference clocks using Xilinx clock generator. At present this has a fixed clock frequency of 30MHz. +
- +
-==== Register access ==== +
- +
-The majority of the parts are accessible via SPI. To keep inside the LPC form factor, the board uses a micro-controller as an I<sup>2</sup>C to SPI bridge (SPI chip selects would have pushed things over the LPC pin count). +
- +
-The reference design SDK sample program provides general spi read and write access. It is possible to expand the access for burst mode.  +
-^ FMC connector ^ I2C Slave Address ^ +
-| HPC | 0x58 | +
-| LPC  | 0x59 | +
- +
-^ Name ^ Chip Select ^ SPI Mode ^ Comment ^ +
-| AD8366 |  6  | SPI_MODE_0, SPI_3WIRE | VGA | +
-| AD9122 |  0  | SPI_MODE_0 | DAC | +
-| AD9523 |  3  | SPI_MODE_0, SPI_3WIRE | Clock-Dist | +
-| AD9548 |  2  | SPI_MODE_0, SPI_3WIRE | Clock-Sync | +
-| AD9643 |  1  | SPI_MODE_0, SPI_3WIRE | ADC | +
-| ADF4351 |  4  | SPI_MODE_0 | RX PLL | +
-| ADF4351 |  5  | SPI_MODE_0 | TX PLL | +
- +
-=== Transaction settings === +
- +
-This must be done before a read or write: +
- +
-I2C Address (Write)| 0x03 | spi_settings[15:8] | spi_settings[7:0] | chip_select[15:8] | chip_select[7:0] | +
- +
-=== Write data === +
- +
-I2C Address (Write)| 0x04 | data | data | data (up to 62 bytes at once) +
- +
-=== Read data === +
- +
-I2C Address (Read) | data |data | data (up to 62 bytes at once) +
- +
-=== SPI settings === +
- +
-<code> +
-[15:10] Rx Transfer count +
-[6]     3-Wire/4-Wire Count +
-           1 = 3-Wire +
-           0 = 4-Wire +
-[5]     CS state at end of transfer +
-           1 = CS goes high +
-           0 = CS remains low +
-[4]     Sample bit +
-           1 = Input data sampled at end of data output time +
-           0 = Input data sampled at middle of data output time +
-[3]     Clock Select +
-           1 = Transmit occurs on transition from active to idle clock state +
-           0 = Transmit occurs on transition from idle to active clock state +
-[2]     Clock Polarity +
-           1 = Idle state for clock is high +
-           0 = Idle state for clock is low +
-[1:0]   SPI Clock +
-           11 = Invalid +
-           10 = Fosc / 64 +
-           01 = Fosc / 16 +
-           00 = Fosc / 4 +
-</code> +
- +
-=== SPI settings chip select === +
- +
-<code> +
-And chip_select is 2^(chip select-1). This is a bitmap. +
-This allows to address multiple parts at once. +
-So the first chip select is 0x0001, the second is 0x0002, the third is 0x0004, etc. +
-</code> +
- +
-=== Preprocessor defines === +
- +
-<code c> +
-#define SPI_XCOMM_SETTINGS_LEN_MASK (0x3f << 10) +
-#define SPI_XCOMM_SETTINGS_3WIRE BIT(6) +
-#define SPI_XCOMM_SETTINGS_CS_HIGH BIT(5) +
-#define SPI_XCOMM_SETTINGS_SAMPLE_END BIT(4) +
-#define SPI_XCOMM_SETTINGS_CPHA BIT(3) +
-#define SPI_XCOMM_SETTINGS_CPOL BIT(2) +
-#define SPI_XCOMM_SETTINGS_CLOCK_DIV_MASK 0x3 +
-#define SPI_XCOMM_SETTINGS_CLOCK_DIV_64 0x2 +
-#define SPI_XCOMM_SETTINGS_CLOCK_DIV_16 0x1 +
-#define SPI_XCOMM_SETTINGS_CLOCK_DIV_4 0x0 +
- +
-#define SPI_XCOMM_CMD_UPDATE_CONFIG 0x03 +
-#define SPI_XCOMM_CMD_WRITE 0x04 +
-</code> +
- +
-==== Power ==== +
- +
-Key components:\\ +
- +
-  * **[[adi>ADP2323]]**, Dual 3A, 20V step-down switcher. +
-  * **[[adi>ADP7104]]**, High accuracy, 500mA LDO +
-  * **[[adi>ADP150/1]]**, Ultra low noise, 150/200 mA LDO +
-  * **[[adi>ADP1740]]**, Low VIN, 2A LDO +
- +
-The board receives all the power from the FPGA board through FMC. +
- +
-==== Optional add-on boards ==== +
- +
-While the board does have the power (+7dBm) to transmit across the room for learning purposes, if you want to drive things at a higher power level, the transmit path may be followed by an optional off board [[adi>ADL5605]] 700 MHz to 1000 MHz, 1 W RF Driver Amplifier, or [[adi>ADL5606]], 1800 MHz to 2700 MHz, 1 W RF Driver Amplifier amplifier to drive the antenna for ISM based communication standards. +
- +
-To increase receive sensitivity, the receive path may be driven by an optional off board [[adi>ADL5523]], which is a 400 MHz to 4000 MHz Low Noise GaAs pHEMT Amplifier. This provides high gain and low noise figure for single-down conversion IF sampling receiver architectures as well as direct-down conversion receivers. +
- +
-===== System specifications ===== +
- +
-HW Platform(s) required: +
-  * One of the following baseboards: +
-    * [[http://www.xilinx.com/ml605|Virtex-6 ML605 (Xilinx)]] +
-    * [[http://www.xilinx.com/kc705|Kintex-7 KC705 (Xilinx)]] +
-    * [[http://www.xilinx.com/vc707|Virtex-7 VC707 (Xilinx)]]   +
-    * [[http://www.xilinx.com/zc702|Zynq ZC702 (Xilinx)]] +
-  * The analog front end hardware platform: +
-    * AD-FMCOMMS1 EBZ (ADI) +
- +
-**System:** Microblaze/ARM (Zynq), AXI, UART. +
- +
-===== Quick Start Guide ===== +
- +
-The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). In order to analyze the signals and the receive path, you will need a spectrum analyzer, signal generator and chipscope. +
- +
-==== Required Hardware ==== +
- +
-  * ML605/KC705/VC707 or ZC702 board  +
-  * AD-FMCOMMS1-EBZ board +
-  * Optional hardware +
-    * Signal generator (~2.4GHz) +
-    * Spectrum analyzer (~2.4GHz) +
- +
-==== Required Software ==== +
- +
-  * Xilinx ISE (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). Please use a version the same as or higher than the one used in the reference design. +
-  * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600. +
-  * Chipscope for busplot of received signals. +
- +
-==== Bit file ==== +
- +
-  * Download the gzip file and extract the **sw/cf_xcomm_<board>.bit** file. +
- +
-==== Running Demo (SDK) Program ==== +
- +
-If you are using the ZC702 board, you will need SDK/XMD to run the demo elf file. Use the following commands to run the demo program. +
- +
-  - fpga -debugdevice devicenr 2 -f cf_xcomm_zc702.bit +
-  - connect arm hw +
-  - source ps7_init.tcl +
-  - ps7_init +
-  - dow cf_xcomm_zc702.elf +
-  - run +
-  - disconnect 64 +
-  - exit +
- +
-A typical XMD transcript is shown below (the commands are highlighted). +
- +
-{{:resources:fpga:xilinx:fmc:cf_xcomm_zc702_xmd.jpg?200|XMD Terminal}} +
- +
-If XMD commands were successful, you will see the UART **__(baud rate 115200 for Zynq Boards)__** window messages as below. For ML605, KC705 and VC707 set the baud rate to 57600. The only difference in Zynq and non-Zynq boards are that the Zynq boards include the HDMI display cores. +
- +
-{{:resources:fpga:xilinx:fmc:cf_xcomm_zc702_uart.jpg?200|UART Terminal}} +
- +
-<note important>For Zynq devices, the demo program runs two sections, first the HDMI and then the XCOMM part. After you start hearing audio clicks, press 'q' and 'enter' on the terminal to start the XCOMM part.</note> +
- +
-If you are using non-zynq device board, program the downloaded bit file and you should see the same messages appear on the UART **__(baud rate 57600)__** window but no HDMI. +
- +
-The DAC outputs for 70MHz/90MHz (2.330GHz/2.310GHz centered at 2.4GHz) tones is shown below. +
- +
-{{:resources:fpga:xilinx:fmc:cf_xcomm_kc705_spectrum.jpg?200|Spectrum Analyzer}} +
- +
-The ADC bus plots on chipscope is shown below, the fft core stores the data (upto 1024) for display and may be viewed anytime when FFT core is idle. The first sample is synchronized with trigger port 0. The plot below scales and offsets the signals to make the display less crowded. +
- +
- +
-| Chipscope Data Ports   | Signal Name       |   Radix          | +
-| DataPort[15:0]         | adc_data_0[15:0]  | signed decimal   | +
-| DataPort[31:16]        | adc_data_0[15:0]  | signed decimal   | +
-| DataPort[47:32]        | hann_window[15:0] | unsigned decimal | +
-| DataPort[63:48]        | fft_input[15:0]   | signed decimal  (real part only) | +
-| DataPort[79:64]        | fft_output[15:0]  | unsigned decimal (magnitude only) | +
- +
-{{:resources:fpga:xilinx:fmc:cf_xcomm_kc705_chipscope.jpg?200|Chipscope Plot}} +
- +
- +
- +
- +
-===== Using the reference design ===== +
- +
-The reference design is a combination of hardware (the FMComms1 Card + the FPGA base platform), the HDL, and the software that is either running on the Microblaze, or ARM Cores. +
- +
-In all the demos that we support, Linux is a large piece. +
- +
-==== Linux Device Drivers ==== +
- +
-  * [[resources:tools-software:linux-drivers:iio-pll:ad9523 | AD9523-1:  Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs]] +
-  * [[resources:tools-software:linux-drivers:iio-pll:adf4350 | ADF4351:  Wideband Synthesizer with Integrated VCO]] +
-  * [[resources:tools-software:linux-drivers:iio-amplifiers:ad8366 | AD8366:  DC to 600 MHz, Dual-Digital Variable Gain Amplifiers]] +
-==== Booting Linux ==== +
-Normally, when the Linux image is booted, it will search both the LPC and HPC FMC slots for 2 cards. (the same reference design supports MIMO, as a single card). You should see something like this in the kernel log message - which indicates that a single card is plugged into the LPC FMC connector. +
- +
-<xterm> +
-# **dmesg** +
-[snip] +
-cf_ad9467 73000000.cf-ad9643-core-lpc: Device Tree Probing 'cf-ad9643-core-lpc' +
-cf_ad9467 73000000.cf-ad9643-core-lpc: ADI AIM (0x10061) at 0x73000000 mapped to 0xe0160000, DMA-0 probed ADC AD9643 as MASTER +
-cf_ad9467 73010000.cf-ad9643-core-hpc: Device Tree Probing 'cf-ad9643-core-hpc' +
-cf_ad9467 73010000.cf-ad9643-core-hpc: Unrecognized CHIP_ID 0xFFFFFFFB +
-iio iio:device2: write failed (-5) +
-ad8366: probe of spi1.6 failed with error -5 +
-ad9548 spi0.2: Rev. 0xC6 probed +
-ad9548: probe of spi1.2 failed with error -5 +
-ad9523 spi0.3: probed ad9523-lpc +
-iio iio:device3: write failed (-5) +
-ad9523: probe of spi1.3 failed with error -5 +
-adf4350: probe of spi1.4 failed with error -5 +
-adf4350: probe of spi1.5 failed with error -5 +
-cf_ad9122 73020000.cf-ad9122-core-lpc: Device Tree Probing 'cf-ad9122-core-lpc' +
-platform 73020000.cf-ad9122-core-lpc: Driver cf_ad9122 requests probe deferral +
-cf_ad9122 73030000.cf-ad9122-core-hpc: Device Tree Probing 'cf-ad9122-core-hpc' +
-platform 73030000.cf-ad9122-core-hpc: Driver cf_ad9122 requests probe deferral +
-ad9122 spi1.0: Unrecognized CHIP_ID 0xFFFFFFFB +
-TCP cubic registered +
-NET: Registered protocol family 17 +
-cf_ad9122 73030000.cf-ad9122-core-hpc: Device Tree Probing 'cf-ad9122-core-hpc' +
-platform 73030000.cf-ad9122-core-hpc: Driver cf_ad9122 requests probe deferral +
-cf_ad9122 73020000.cf-ad9122-core-lpc: Device Tree Probing 'cf-ad9122-core-lpc' +
-Freeing unused kernel memory: 2933k freed +
-cf_ad9122 73020000.cf-ad9122-core-lpc: Analog Devices AD9122_DDS MASTER (0x10061) at 0x73020000 mapped to 0xe01a0000, probed DDS AD9122 +
-cf_ad9122 73030000.cf-ad9122-core-hpc: Device Tree Probing 'cf-ad9122-core-hpc' +
-platform 73030000.cf-ad9122-core-hpc: Driver cf_ad9122 requests probe deferral +
-cf_ad9122 73030000.cf-ad9122-core-hpc: Device Tree Probing 'cf-ad9122-core-hpc' +
-platform 73030000.cf-ad9122-core-hpc: Driver cf_ad9122 requests probe deferral +
-</xterm> +
- +
-You can also check the status of things with: +
-<xterm># **cat /sys/bus/iio/devices/*/name** +
-cf-ad9643-core-lpc +
-ad8366-lpc +
-ad9523-lpc +
-adf4351-rx-lpc +
-adf4351-tx-lpc +
-cf-ad9122-core-lpc +
-</xterm> +
- +
-Those are the devices that the Linux kernel found. +
- +
-==== Running the demo ==== +
- +
-It's a simple matter of configuring the ethernet on the FPGA platform: +
-<xterm># **ifconfig eth0 192.168.1.2 up** +
-# **ifconfig eth0** +
-eth0      Link encap:Ethernet  HWaddr 00:0A:35:69:1C:00   +
-          inet addr:192.168.1.2  Bcast:192.168.1.255  Mask:255.255.255.0 +
-          UP BROADCAST RUNNING  MTU:1500  Metric:1 +
-          RX packets:11 errors:0 dropped:0 overruns:0 frame:0 +
-          TX packets:1 errors:0 dropped:0 overruns:0 carrier:0 +
-          collisions:0 txqueuelen:1000  +
-          RX bytes:3506 (3.4 KiB)  TX bytes:322 (322.0 B) +
-          Interrupt:10 Memory:40e00000-40e0ffff  +
-</xterm> +
-(or by running the udhcpc client) +
- +
-and then ensuring that the your host PC is attached to the same subnet as the FPGA platform. +
- +
-{{:resources:fpga:xilinx:fmc:scope.png?400|}} +
- +
-From here you can look at things in the time domain, frequency domain, and control the various "knobs" in the platform. +
- +
-To find the various "knobs", they are in the ''sysfs'' directory. +
-<xterm> +
-# **cd /sys/devices/axi.0/40800000.i2c/i2c-0/0-0059/spi_master/spi0/spi0.3/iio:device2** +
-# **ls** +
-dev +
-name +
-out_altvoltage0_ZD_OUTPUT_frequency +
-out_altvoltage0_ZD_OUTPUT_phase +
-out_altvoltage0_ZD_OUTPUT_raw +
-out_altvoltage0_clk_src_vcxo_en +
-out_altvoltage1_DAC_CLK_frequency +
-out_altvoltage1_DAC_CLK_phase +
-out_altvoltage1_DAC_CLK_raw +
-out_altvoltage1_clk_src_vcxo_en +
-out_altvoltage2_ADC_CLK_frequency +
-out_altvoltage2_ADC_CLK_phase +
-out_altvoltage2_ADC_CLK_raw +
-out_altvoltage2_clk_src_vcxo_en +
-out_altvoltage3_clk_src_vcxo_en +
-out_altvoltage4_DAC_REF_CLK_frequency +
-out_altvoltage4_DAC_REF_CLK_phase +
-out_altvoltage4_DAC_REF_CLK_raw +
-out_altvoltage4_clk_src_vco2_en +
-out_altvoltage5_TX_LO_REF_CLK_frequency +
-out_altvoltage5_TX_LO_REF_CLK_phase +
-out_altvoltage5_TX_LO_REF_CLK_raw +
-out_altvoltage5_clk_src_vco2_en +
-out_altvoltage6_DAC_DCO_CLK_frequency +
-out_altvoltage6_DAC_DCO_CLK_phase +
-out_altvoltage6_DAC_DCO_CLK_raw +
-out_altvoltage6_clk_src_vco2_en +
-out_altvoltage7_clk_src_vco2_en +
-out_altvoltage8_ADC_SYNC_CLK_frequency +
-out_altvoltage8_ADC_SYNC_CLK_phase +
-out_altvoltage8_ADC_SYNC_CLK_raw +
-out_altvoltage8_clk_src_vco2_en +
-out_altvoltage9_RX_LO_REF_CLK_frequency +
-out_altvoltage9_RX_LO_REF_CLK_phase +
-out_altvoltage9_RX_LO_REF_CLK_raw +
-out_altvoltage9_clk_src_vco2_en +
-status +
-store_eeprom +
-subsystem +
-sync +
-uevent +
-vco1_frequency +
-vco2_frequency +
-vco_frequency_available +
-</xterm> +
- +
-You can ''echo'' or ''cat'' into these files to change the various options. +
- +
-<xterm> +
-# **cat out_altvoltage1_DAC_CLK_frequency** +
-491520000 +
-# **echo 500000000 > out_altvoltage1_DAC_CLK_frequency** +
-# **cat out_altvoltage1_DAC_CLK_frequency** +
-983040000 +
-# **echo 400000000 > out_altvoltage1_DAC_CLK_frequency** +
-# **cat out_altvoltage1_DAC_CLK_frequency** +
-491520000 +
-</xterm> +
- +
-Just like if you were trying to program the part with specific frequencies, there are only so many options you can pick, so it attempts to pick the "closest" option. +
-==== Functional description ==== +
- +
-===== Downloads ===== +
-<WRAP alert>Although we think Reb B fixes all the issues - it is still under evaluation. However - some people wanted to look at the scheamtics early - here you go.</WRAP> +
-  * {{:resources:fpga:xilinx:fmc:fmcomms1-revbschematic.pdf|Schematic}} +
- +
- +
-FPGA Referece Designs: +
- +
-  * {{:resources:fpga:xilinx:fmc:cf_xcomm_kc705.tar.gz|KC705 Tar Gzip}} +
-  * {{:resources:fpga:xilinx:fmc:cf_xcomm_zc702.tar.gz|ZC702 Tar Gzip}} +
-  * {{:resources:fpga:xilinx:fmc:cf_xcomm_zed.tar.gz|ZED Tar Gzip}} +
- +
-The GZip file will not contain Xilinx core generator and IP files. You must obtain these files from Xilinx. +
-===== Tar file contents ===== +
- +
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build  +
-the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details. +
- +
-In the case of Zynq, the same procedure applies, except that you must create a FSBL or run the PS7 initialization tcl scripts before the SDK program.+
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
Line 440: Line 59:
 | sw/         | Software (Xilinx SDK) & bit file(s). | | sw/         | Software (Xilinx SDK) & bit file(s). |
 | cf_lib/edk/pcores | pcores (if used). | | cf_lib/edk/pcores | pcores (if used). |
- 
-===== More information ===== 
- 
-  * [[http://www.vita.com/fmc.html|VITA's FMC info]] 
-  * [[ez>community/fpga|ask questions about the Board, or the FPGA reference design]] 
-  * As soon as released, will include purchasing information 
- 
- 
- 

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