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+ | ====== AD-FMCOMMS1-EBZ HDL Reference Design ====== | ||
+ | ===== Supported Devices ===== | ||
+ | |||
+ | * [[adi> | ||
+ | |||
+ | ===== Supported Carriers ===== | ||
+ | |||
+ | * [[xilinx> | ||
+ | * [[xilinx> | ||
+ | * [[xilinx> | ||
+ | * [[xilinx> | ||
+ | * [[xilinx> | ||
+ | * [[http:// | ||
+ | |||
+ | ===== Download ====== | ||
+ | |||
+ | FPGA Reference Designs on GitHub : | ||
+ | |||
+ | <WRAP round info 80%> | ||
+ | The reference designs has been updated to the latest register map and pcores. This is a major change is NOT compatible with the older version. Please be careful in choosing the right version. Please consider updating to the new versions if you are still using the old version. | ||
+ | </ | ||
+ | |||
+ | <WRAP round download 80%> | ||
+ | * HDL version 2.0 | ||
+ | * https:// | ||
+ | * https:// | ||
+ | |||
+ | </ | ||
+ | |||
+ | <WRAP round download 80%> | ||
+ | * HDL version 1.0 | ||
+ | * https:// | ||
+ | * https:// | ||
+ | * https:// | ||
+ | * https:// | ||
+ | </ | ||
+ | |||
+ | <WRAP round download 80%> | ||
+ | * Git Repository, Releases and Tags | ||
+ | * https:// | ||
+ | * https:// | ||
+ | </ | ||
+ | |||
+ | <WRAP round help 80%> | ||
+ | * Questions? [[http:// | ||
+ | </ | ||
+ | |||
+ | ===== Generating Xilinx netlist files ====== | ||
+ | |||
+ | The repository will not contain Xilinx netlist files. If you need to build the design, you must generate these files. The following steps illustrate the process using coregen. | ||
+ | |||
+ | |||
+ | |Open coregen, the default path is " | ||
+ | |If you have an existing project file, use that. Otherwise click " | ||
+ | |Pick a directory location in this case it is " | ||
+ | |Under the " | ||
+ | |Under the " | ||
+ | |Now we need the list of modules to generate the netlist files. The repository contains xco files for each of the netlist file that is missing. A windows search for " | ||
+ | |In coregen, select " | ||
+ | |Change the view (left bottom) to " | ||
+ | |Select " | ||
+ | |Once complete, copy the " | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | ==== Tar file contents ==== | ||
+ | |||
+ | The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. Please refer to [[http:// | ||
+ | |||
+ | | license.txt | ADI license & copyright information. | | ||
+ | | system.mhs | ||
+ | | system.xmp | ||
+ | | data/ | UCF file and/or DDR MIG project files. | | ||
+ | | docs/ | Documentation files (Please note that this wiki page is the documentation for the reference design). | | ||
+ | | sw/ | Software (Xilinx SDK) & bit file(s). | | ||
+ | | cf_lib/ |