Table of Contents
AD-FMCOMMS1-EBZ HDL Reference Design
FPGA Reference Designs on GitHub :
- Vivado Downloads
- Main repository with latest changes (may be unstable)
- The latest stable version for Vivado 2014.2
- Previous release for Vivado 2013.4
We strongly recommend using the Vivado designs, as all development has moved to Vivado. The XPS reference design has been updated to the latest register map and pcores (HDL version 2). This is a major change is NOT compatible with version 1. Please be careful in choosing the right version. Please consider updating to the new versions if you are still using the old version.
- HDL version 2.0
- HDL version 1.0
- Git Repository, Releases and Tags
- Questions? Ask Help & Support.
Generating Xilinx netlist files
The repository will not contain Xilinx netlist files. If you need to build the design, you must generate these files. The following steps illustrate the process using coregen.
Tar file contents
The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. Please refer to Xilinx EDK documentation for details.
|license.txt||ADI license & copyright information.|
|system.xmp||XMP file (use this file to build the reference design).|
|data/||UCF file and/or DDR MIG project files.|
|docs/||Documentation files (Please note that this wiki page is the documentation for the reference design).|
|sw/||Software (Xilinx SDK) & bit file(s).|
|cf_lib/edk/pcores||pcores (if used).|