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====== CED1Z FPGA Project for ADAS3023 with Nios driver  ======

====== Overview ======

This document presents the steps to setup an environment for using the **[[adi>EVAL-ADAS3023| EVAL-ADAS3023EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]**, the Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-ADAS3023EDZ Evaluation Board with the CED1 board.

{{ :resources:fpga:altera:ced1z:ced1z_adas3022.png?500 }}

The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link.

The [[adi>ADAS3023]] is a complete 16-bit successive approximation based analog-to-digital data acquisition system. This device is capable of simultaneously sampling up to 500 kSPS for two channels, 250 kSPS for four channels, 167 kSPS for six channels, and 125 kSPS for eight channels manufactured on the Analog Devices, Inc., proprietary iCMOS® high voltage industrial process technology.
The ADAS3023 integrates an 8-channel low leakage track and hold, a programmable gain instrumentation amplifier (PGIA) stage with a high common-mode rejection offering four differential input ranges, a precision low drift 4.096 V reference and buffer, and a 16-bit charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC). The ADAS3023 can resolve differential input ranges of up to ±20.48 V when using ±15 V supplies.

The **EVAL-ADAS3023EDZ** evaluation board is designed to help customers quickly prototype new ADAS3023 circuits and reduce design time.

===== More information =====

  * [[adi>ADAS3023|ADAS3023 Product Info]] - pricing, samples, datasheet
  * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]

====== Getting Started ======

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

===== Hardware Items =====

Below is presented the list of required hardware items:
  * Analog Devices [[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]
  * [[http://www.terasic.com.tw/|Terasic USB Blaster]]
  * **EVAL-ADAS3023EDZ** evaluation board
  * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory

===== Software Tools =====

Below is presented the list of required software tools:
  * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0
  * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0

The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web.

===== Downloads =====

  * {{:resources:fpga:altera:ced1z:adas3023_evalboard.zip|Evaluation Project Files}}

===== Extract the Lab Files =====

Create a folder called “**//ADIEvalBoard//**” on your PC and extract the **//adas3023_evalboard.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoard//** folder: **//EvalBoardFPGA//**, **//FPGA//**, **//Hdl//**, **//NiosCpu//**, **//Software//**, **//DataCapture//**

^ **Folder** ^ **Description** ^
| EvalBoardFPGA | Contains the reference project which is loaded on the EVAL-ADAS3023EDZ board. The ADAS3023.v file contains the main ADC driver module |
| FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script //program_fpga.bat// the FPGA will be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder. \\ The //ip// subfolder contains the HDL core for connecting the evaluation board to the CED1Z board , the software drivers for HAL in ///hdl/src/HAL// and the ADAS3023 registers in ///hdl/src/inc//  |
| Hdl | Contains the source files for the ADAS3023 core : \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files. |
| NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the ADAS3023 SOPC component |
| Software | Contains the source files of the Nios2 SBT evaluation project |
| DataCapture | Contains the script files used for data acquisition |

===== Install the USB-Blaster Device Driver =====

{{page>:resources:fpga:altera:ced1z:common_usb}}

======= ADAS3023 Evaluation Project Overview =======

The evaluation project contains all the source files needed to build a system that can be used to configure the ADAS3023 and capture data from it. The system consists of a Nios II softcore processor that is implemented in the FPGA found on the CED1Z board and a PC application. The softcore controls the communication with the Device Under Test (DUT) and the data capture process. The captured data is saved into the SRAM of the CED1Z board and aftwerwards it is read by the PC application and saved into a comma separated values (.csv) file that can be used for further data analysis.

===== FPGA Design =====

The following components are implemented in the FPGA design:

^ Name                   ^ Address         ^ IRQ       ^
| CPU                    | 0x00000800      | -         |
| PLL                    | 0x00000000      | -         |
| ONCHIP_MEM             | 0x00002000      | -         |
| LEDS                   | 0x00000010      | -         |
| SYSID                  | 0x00000020      | -         |
| SRAM                   | 0x00200000      | -         |
| TRISTATE_BRIDGE_0      | -               | -         |
| UCPROBE_UART           | 0x00000028      | 0         |
| JTAG_UART_0            | 0x00000030      | 1         |
| SYS_TIMER              | 0x00000040      | 2         |
| MM_CONSOLE_MASTER      | -               | -         |
| PWR_DATA               | 0x00000060      | -         |
| I2C_INT                | 0x00000080      | -         |
| PWR_EN_CLK             | 0x000000a0      | -         |
| ADAS3023_0             | 0x000000c0      | -         |
|  **Table 1 System components**  |||

The Nios II processor contains a peripheral that implements the communication protocol with the DUT. The peripheral is divided into three logical modules: a module which implements the interface with the Avalon bus , a module which implements an Avalon master interface which is used to write data directly in the SRAM and a module which communicates with the evaluation board. Following is presented a block diagram of the HDL core and a description of the interface signals.

{{ :resources:fpga:altera:ced1z:adas3023_core_pinout.png?500 |Avalon core pinout diagram}}

Table 2 describes the port definitions of the Avalon peripheral:

^ Port ^ Direction ^ Width ^ Description ^
| //**Generic pins**// ||||
| CLK_I                     | IN  | 1  | Main clock input |
| RESET_I                   | IN  | 1  | System reset |
| //**Avalon Slave Interface**// ||||
| AVALON_WRITEDATA_I        | IN  | 32 | Slave write data bus |
| AVALON_WRITE_I            | IN  | 1  | Slave write data request |
| AVALON_READ_I             | IN  | 1  | Slave read data request |
| AVALON_ADDRESS_I          | IN  | 2  | Slave address bus |
| AVALON_READDATA_O         | OUT | 32 | Slave read data bus|
| //**Avalon Master Interface**// ||||
| AVALON_MASTER_WAITREQUEST | IN  | 1  | Master wait request signal |
| AVALON_MASTER_ADDRESS_O   | OUT | 32 | Master address bus |
| AVALON_MASTER_BYTEENABLE_O| OUT | 4  | Master byte enable signals |
| AVALON_MASTER_WRITEDATA_O | OUT | 32 | Master write data bus |
| //**External connectors**// ||||
| BBUSY_I                | IN  | 1  | Signal that indicates the status of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes high |
| BDB_IO                 | I/O | 16 | Bidirectional data bus used to write/read data to/from the ADAS3023_EDZ board |
| BRD_N_O                | OUT | 1  | Signal used by the CED1Z board to read data from the ADAS3023_EDZ board |
| BWR_N_O                | OUT | 1  | Signal used by the CED1Z board to write data to the ADAS3023_EDZ board |
| BRESET_O               | OUT | 1  | Used to reset the evaluation board |
| BADDR_O                | OUT | 5  | Used to select the register to be read from the ADAS3023_EDZ board. |
|  **Table 2 Port description**  ||||

Table 3 describes the registers of the Avalon peripheral:

^ Name ^ Offset ^ Width ^ Access ^ Description ^
| CONTROL_REGISTER          | 0  | 32  | RW | Bit 0 is used to start data acquisition \\ Bit 1 is used to initiate software reset of the core \\ Bit 2 is used to configure the Avalon write master core to write data to the same location \\ Bit 3 is used to write data to the ADAS3023 evaluation board|
| ACQ_COUNT_REGISTER        | 1  | 32  | RW | Register used to configure the number of samples to be acquired when acquisition is started |
| BASE_REGISTER             | 2  | 32  | RW | Register used to configure the base address of the memory location where the acquired data is to be written |
| STATUS                    | 3  | 32  | R  | Bit 0 is used to signal that the acquisition is complete \\ Bit 1 is used to signal that the internal memory buffer has been overflown \\ Bit 2 is used to signal that the user has performed a write of a read only register register|
| DUT_WRITE_REGISTER        | 4  | 32  | W  | Register used to perform writes on the device under test. Bits [15:0] are used for data and [20:16] are used as address. The rest are discarded |
|  **Table 3 Register description**  |||||

===== ADAS3023 HDL driver =====

In order to acquire data from the ADAS3023, several modules are implemented on the Evaluation Board FPGA.

{{ :resources:fpga:altera:ced1z:adas3023edz_system.png?800 | Evaluation board driver overview}}

The ADAS3023 module is the actual driver of the ADAS3023 data acquisition system.

{{ :resources:fpga:altera:ced1z:adas3023_pinout.png?500 | ADAS3023 module pinout}}

^ Port ^ Direction ^ Width ^ Description ^
| //**Generic connectors**// ||||
| FPGA_CLK_I                | IN  | 1  | 100 MHz clock |
| RESET_I                   | IN  | 1  | Module reset |
| //**CED1Z_interface connectors**// ||||
| WR_DATA_N_I               | IN  | 1  | Signal used to write data in the driver’s internal registers, data which will be sent to the ADAS3023 |
| DATA_I                    | IN  | 16 | Data bus, used to send new configuration words to the ADAS3023 |
| DATA_CHANNELS_O           | OUT | 128| Parallel port to transfer the data to the CED1Z_interface module |
| DATA_RD_READY_O           | OUT | 1  | Signals that at port DATA_O there is new data available |
| DATA_WR_READY_O           | OUT | 1  | Signals that the write from CED1Z_interface module has been performed |
| ACQ_ERROR_O               | OUT | 1  | signals that there was an error during acquisition and the sampling period may not be met |
| //**ADAS3023 connectors**// ||||
| MISO_I                    | IN  | 1  | Signal connected to the SDO pin of the ADAS3023 |
| BUSY_I                    | IN  | 1  | Signal connected to the BUSY pin of the ADAS3023 |
| MOSI_O                    | OUT | 1  | Signal connected to the DIN pin of the ADAS3023 |
| SCLK_O                    | OUT | 1  | Signal connected to the SCK pin of the ADAS3023. 50 MHz clock |
| SS_N_O                    | OUT | 1  | Signal connected to the CS_N pin of the ADAS3023 |
| CNV_O                     | OUT | 1  | Signal connected to the CNV pin of the ADAS3023 |
| RESET_O                   | OUT | 1  | Signal connected to the RESET pin of the ADAS3023 |
| PD_O                      | OUT | 1  | Signal connected to the PD pin of the ADAS3023 |
|  **Table 3 Port description for the ADAS3023 module**  ||||

The CED1Z_interface module is used to communicate with the CED1Z board.
The PLL module is used to generate 100MHz clock signal from the 100MHz external clock signal available on the evaluation board.

====== Quick Evaluation ======

The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/FPGA folder.

The Evaluation Board design presented on this page is different than the default design loaded on the ADAS3023EDZ. In order to use the design from this page, the Evaluation Board FPGA must be reprogrammed. To reprogram the FPGA on the Evaluation board, the following steps must be followed, AFTER the CED1Z FPGA has been programmed using program_fpga.bat:
  * 1. Connect the USB-Blaster to the P2 port
  * 2. Start Quartus II, Start Tools ->Programmer
  * 3. Select Mode Active Serial Programming
  * 4. Press Add File and select EvalBoardFPGA/EvalBoardAdas3023.pof
  * 5. Check Program/Configure and Press Start.
  * 6. After the programming ends, power off the CED1Z and reprogramm it using program_fpga.bat as described above.

<WRAP round help> This is a one time operation, as the programming is done on a non volatile memory on the Evaluation Board. </WRAP>

In order to acquire data, follow the instructions in the //**Evaluation Project Data Acquisition**// section.

====== NIOS II Software Design ======

{{page>:resources:fpga:altera:ced1z:common_software_design}}

====== Evaluation Project Data Acquisition ======

After the FPGA is correctly programmed the data acquisition process can start by executing the data_acquisition.bat script.

The ADAS3023 can be configured by editing the data_capture.tcl script, and configuring each bit of the CONFIGURATION register. Each time the script is changed, the CED1Z must be powered off and reprogrammed. If the data is acquired in WARP mode, the first acquisition may not be correct.

If the resulting csv file is opened with Microsoft Excel, the data will be displayed on a single column if the sequencer is disabled or on 8 columns if the basic sequencer is enabled. Each column represents a channel. If the ADAS3023 is configured to acquire less than 8 channels the remaining channels will have a constant value. For example, in the below picture, the ADAS3023 was configure to acquire data on 4 differential channels, a sine signal was applied on the first channel and the rest were left floating. In this case, the first column can be plotted as a sine wave, the next 3 have some noise on them, and the last 4 have a constant value of 0.

{{ :resources:fpga:altera:ced1z:4chan.png?800 | Plot of acquired data}}

====== More information ======
  * [[ez>community/fpga|ask questions about the FPGA reference design]]
  * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}
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