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====== CED1Z FPGA Project for AD7766-1 with Nios driver  ======

===== Supported Devices =====

  * [[adi>AD7766|AD7766-1]]

===== Evaluation Boards =====

  * [[adi>EVAL-AD7766-1EDZ]]

====== Overview ======

This document presents the steps to setup an environment for using the **[[adi>EVAL-AD7766-1EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]** and Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-AD7766-1 Evaluation Board with the CED1 board.

{{ :resources:fpga:altera:ced1z:ced1z_ad7766.png?500 }}

The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link.

The [[adi>AD7766| AD7766-1]] is a high performance 24-bit oversampled SAR analog-to-digital converter (ADC). The AD7766-1 combines the benefits of a large dynamic range and input bandwidth, consuming  10.5 mW power,  contained in a 16-lead TSSOP package.

===== More information =====

  * [[adi>AD7766|AD7766-1 Product Info]] - pricing, samples, datasheet
  * [[adi>/static/imported-files/eval_boards/EVAL-AD7766_7766-1_7766-2EDZ_PrB.pdf|EVAL-AD7766-1EDZ evaluation board user guide]]
  * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]

====== Getting Started ======

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

===== Hardware Items =====

Below is presented the list of required hardware items:
  * Analog Devices [[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]
  * [[http://www.terasic.com.tw/|Terasic USB Blaster]]
  * **EVAL-AD7766-1EDZ** evaluation board
  * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory

===== Software Tools =====

Below is presented the list of required software tools:
  * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0
  * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0

The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. 

===== Downloads =====
  * {{:resources:fpga:altera:ced1z:ad7766_evalboard.zip|Evaluation Project Files}}


===== Extract the Lab Files =====

Create a folder called “**//ADIEvalBoard//**” on your PC and extract the **//ad7766_evalboard.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoard//** folder: **//FPGA//**, **//Hdl//**, **//NiosCpu//**, **//Software//**, **//DataCapture//**

^ **Folder** ^ **Description** ^
| FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script //program_fpga.bat// the FPGA will be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder. \\ The //ip// subfolder contains the HDL core for connecting the evaluation board to the CED1Z board , the software drivers for HAL in ///hdl/src/HAL// and the AD7766 registers in ///hdl/src/inc//  |
| Hdl | Contains the source files for the AD7766 HDL driver: \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files.  \\ - The //tb// folder contains the sources of the core's testbench |
| NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the AD7766 QSYS component |
| Software | Contains the source files of the Nios2 SBT evaluation project |
| DataCapture | Contains the script files used for data acquisition |

===== Install the USB-Blaster Device Driver =====
{{page>:resources:fpga:altera:ced1z:common_usb}}

======= AD7766-1 Evaluation Project Overview =======

The evaluation project contains all the source files needed to build a system that can be used to configure the AD7766-1 and capture data from it. The system consists of a Nios II softcore processor that is implemented in the FPGA found on the CED1Z board and a PC application. The softcore controls the communication with the Device Under Test (DUT) and the data capture process. The captured data is saved into the SRAM of the CED1Z board and aftwerwards it is read by the PC application and saved into a comma separated values (.csv) file that can be used for further data analysis.

===== FPGA Design =====

The following components are implemented in the FPGA design:

^ Name                   ^ Address         ^ IRQ       ^
| CPU                    | 0x00000800      | -         |
| PLL                    | 0x00000000      | -         |
| ONCHIP_MEM             | 0x00002000      | -         |
| LEDS                   | 0x00000010      | -         |
| SYSID                  | 0x00000020      | -         |
| SRAM                   | 0x00200000      | -         |
| TRISTATE_BRIDGE_0      | -               | -         |
| UCPROBE_UART           | 0x00000028      | 0         |
| JTAG_UART_0            | 0x00000030      | 1         |
| SYS_TIMER              | 0x00000040      | 2         |
| MM_CONSOLE_MASTER      | -               | -         |
| PWR_DATA               | 0x00000060      | -         |
| I2C_INT                | 0x00000080      | -         |
| PWR_EN_CLK             | 0x000000a0      | -         |
| AD7766_0               | 0x000000c0      | -         |
|  **Table 1 System components**  |||

The Nios II processor contains a peripheral that implements the communication protocol with the DUT. The peripheral is divided into three logical modules: a module which implements the interface with the Avalon bus and the communication with the SRAM, a module which implements an Avalon master interface which is used to write data directly in the SRAM and a module which communicates with the evaluation board. Following is presented a block diagram of the HDL core and a description of the interface signals.

{{ :resources:fpga:altera:ced1z:ad7766_core_pinout.png?500 |Avalon core pinout diagram}}

Table 2 describes the port definitions of the Avalon peripheral:

^ Port ^ Direction ^ Width ^ Description ^
| //**Generic pins**// ||||
| FPGA_CLK_I                | IN  | 1  | System clock. Designed with a 98MHz clock |
| ADC_CLK_I                 | IN  | 1  | Clock used for generating SCLK. Designed with a 12 MHz clock |
| ADC_MCLK_I                | IN  | 1  | Clock used for generating MCLK. Designed with 25.6 MHz |
| RESET_I                   | IN  | 1  | System reset |
| //**Avalon Slave Interface**// ||||
| AVALON_WRITEDATA_I        | IN  | 32 | Slave write data bus |
| AVALON_WRITE_I            | IN  | 1  | Slave write data request |
| AVALON_READ_I             | IN  | 1  | Slave read data request |
| AVALON_ADDRESS_I          | IN  | 2  | Slave address bus |
| AVALON_READDATA_O         | OUT | 32 | Slave read data bus|
| //**Avalon Master Interface**// ||||
| AVALON_MASTER_WAITREQUEST | IN  | 1  | Master wait request signal |
| AVALON_MASTER_ADDRESS_O   | OUT | 32 | Master address bus |
| AVALON_MASTER_BYTEENABLE_O| OUT | 4  | Master byte enable signals |
| AVALON_MASTER_WRITEDATA_O | OUT | 32 | Master write data bus |
| //**External connectors**// ||||
| ADC_SDO_I                 | IN  | 1  | ADC’s SDO pin. |
| ADC_DRDY_N_I              | IN  | 1  | ADC’s Data Ready pin. |
| ADC_MCLK_O                | OUT | 1  | ADC’s MCLK pin. Designed with 1.024MHz. |
| ADC_SCLK_O                | OUT | 1  | ADC’s SCLK pin. Designed with 12MHz. |
| ADC_SDI_O                 | OUT | 1  | ADC’s SDI pin. Connected to ground in this design. |
| ADC_CS_N_O                | OUT | 1  | ADC’s Chip Select pin.  |
| ADC_SYNC_PD_N_O           | OUT | 1  | ADC’s SYNC/PD pin. Controlled by the AD7766-1 driver module |
|  **Table 2 Port description**  ||||

Table 3 describes the registers of the Avalon peripheral:

^ Name ^ Offset ^ Width ^ Access ^ Description ^
| CONTROL_REGISTER          | 0  | 32  | RW | Bit 0 is used to start data acquisition \\ Bit 1 is used to initiate software reset of the core \\ Bit 2 is used to configure the Avalon write master core to write data to the same location |
| ACQ_COUNT_REGISTER        | 1  | 32  | RW | Register used to configure the number of samples to be acquired when acquisition is started |
| BASE_REGISTER             | 2  | 32  | RW | Register used to configure the base address of the memory location where the acquired data is to be written |
| STATUS                    | 3  | 32  | R  | Bit 0 is used to signal that the acquisition is complete \\ Bit 1 is used to signal that the internal memory buffer has been overflown \\ Bit 2 is used to signal that the user has performed a write of a read only register register|
|  **Table 3 Register description**  |||||

The follwing figure presents the timing diagram for the read operations from the AD7766-1 driver .

{{ :resources:fpga:altera:ced1z:ad7766_read_timing.png?500 |Read operations time diagram}}

===== AD7766-1 HDL driver =====

The AD7766-1 driver is a submodule of the AD7766 core. The following picture represents the driver pinout:

{{ :resources:fpga:altera:ced1z:ad7766_driver_pinout.png?500 | AD7766-1 driver pinout}}

^ Port ^ Direction ^ Width ^ Description ^
| //**Generic pins**// ||||
| FPGA_CLK_I                | IN  | 1  | System clock. Designed with a 98MHz clock |
| ADC_CLK_I                 | IN  | 1  | Clock used for generating SCLK. Designed with a 12 MHz clock |
| ADC_MCLK_I                | IN  | 1  | Clock used for generating MCLK. Designed with 25.6 MHz |
| RESET_I                   | IN  | 1  | System reset |
| DATA_O                    | OUT | 24 | Data read from the ADC |
| DATA_RD_READY_O           | OUT | 1  | Signals that new data can be read from the DATA_O bus |
| ADC_SDO_I                 | IN  | 1  | ADC’s SDO pin. |
| ADC_DRDY_N_I              | IN  | 1  | ADC’s Data Ready pin. |
| ADC_MCLK_O                | OUT | 1  | ADC’s MCLK pin. Designed with 1.024MHz. |
| ADC_SCLK_O                | OUT | 1  | ADC’s SCLK pin. Designed with 12MHz. |
| ADC_SDI_O                 | OUT | 1  | ADC’s SDI pin. Connected to ground in this design. |
| ADC_CS_N_O                | OUT | 1  | ADC’s Chip Select pin.  |
| ADC_SYNC_PD_N_O           | OUT | 1  | ADC’s SYNC/PD pin. In this design it is activated when the driver is reset |

====== Quick Evaluation ======
{{page>:resources:fpga:altera:ced1z:quick_evaluation}}

====== NIOS II Software Design ======
{{page>:resources:fpga:altera:ced1z:common_software_design}}

====== Evaluation Project User Interface ======

In order to capture data from the ADC the following steps must be performed:
  * Make sure that the //**CED1Z FPGA**// is properly programmed and the USB Blaster is connected to the CED1Z board.
  * Execute //**data_capture.bat**// script. At this point 1 Mbyte of data will be acquired from the ADC and saved into the CED1Z SRAM memory. The data stored in the CED1Z SRAM memory is transfered to the PC through the JTAG-UART link provided by the USB Blaster. After the data is transferred to the PC it is converted to 2's Complement 24 bit values.
  * The resulting data is saved into a comma separated values (.csv) file named **//Acquisition.csv//**, located in the same folder as the //**data_capture.bat**// file.
  * The data capture status is also displayed in the opened command window as shown in the figure below.

{{ :resources:fpga:altera:cedz:cmd_interface.png?500 |Demonstration Project Command Interface}}
  * A new acquisition can be started by executing the //**data_capture.bat**// script.

//**Note:**// If several consecutive data acquisitions are performed the captured data is appended to the **//Acquisition.csv//** file.

====== More information ======
  * [[ez>community/fpga|ask questions about the FPGA reference design]]
  * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}
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