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====== CED1Z FPGA Project for AD7689 with Nios driver  ======

===== Supported Devices =====

  * [[adi>AD7689]]

===== Evaluation Boards =====

  * [[adi>EVAL-AD7689EDZ]]

====== Overview ======

This document presents the steps to setup an environment for using the **[[adi>AD7689|EVAL-AD7689EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]**, the Nios II Embedded Development Suite (EDS) and the [[https://www.micrium.com/ucprobe/about/|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD7689 Evaluation Board with the CED1 board.

{{ :resources:fpga:altera:ced1z:ced1z_ad7689.png?500 }}

The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link.

The [[adi>AD7689| AD7689]] is a 8-channel, 16-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) that operates from a single power supply.
The AD7689 contains all components for use in a multichannel, low power data acquisition system, including a true 16-bit SAR ADC with no missing codes; an 8-channel, low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order.

===== More information =====

  * [[adi>AD7689|AD7689 Product Info]] - pricing, samples, datasheet
  * [[adi>/static/imported-files/eval_boards/EVAL-AD76MUXEDZ.pdf|EVAL-AD76MUXEDZ evaluation board user guide]]
  * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]
  * [[https://www.micrium.com/ucprobe/about/|Micrium uC-Probe]]

====== Getting Started ======

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

===== Hardware Items =====

Below is presented the list of required hardware items:
  * Analog Devices [[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]
  * [[http://www.terasic.com.tw/|Terasic USB Blaster]]
  * **EVAL-AD7689EDZ** evaluation board
  * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory

===== Software Tools =====

Below is presented the list of required software tools:
  * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0
  * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0

The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. 

===== Downloads =====

  * {{:resources:fpga:altera:ced1z:ad7689_evalboard.zip|Evaluation Project Files}}


===== Extract the Lab Files =====

Create a folder called “**//ADIEvalBoard//**” on your PC and extract the **//ad7689_evalboard.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoard//** folder: **//EvalBoardFPGA//**, **//FPGA//**, **//Hdl//**, **//NiosCpu//**, **//Software//** and **//DataCapture//** .
^ **Folder** ^ **Description** ^
| EvalBoardFPGA | Contains the reference project which is loaded on the EVAL-AD689EDZ board. The AD7689.v file contains the main ADC driver modules |
| FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script //program_fpga.bat// the FPGA will be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder. \\ The //ip// subfolder contains the HDL core for connecting the evaluation board to the CED1Z board , the software drivers for HAL in ///hdl/src/HAL// and the AD7689 registers in ///hdl/src/inc//  |
| Hdl | Contains the source files for the AD7689 HDL driver: \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files.  \\ - The //tb// folder contains the sources of the core's testbench |
| NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the AD7689 QSYS component |
| Software | Contains the source files of the Nios2 SBT evaluation project |
| DataCapture | Contains the script files used for data acquisition |

===== Install the USB-Blaster Device Driver =====

{{page>:resources:fpga:altera:ced1z:common_usb}}

======= AD7689 Evaluation Project Overview =======

The evaluation project contains all the source files needed to build a system that can be used to configure the AD7689 and capture data from it. The system consists of a Nios II softcore processor that is implemented in the FPGA found on the CED1Z board and a PC application. The softcore controls the communication with the Device Under Test (DUT) and the data capture process. The captured data is saved into the SRAM of the CED1Z board and aftwerwards it is read by the PC application and saved into a comma separated values (.csv) file that can be used for further data analysis.

===== CED1Z FPGA Design =====

The following components are implemented in the FPGA design:

^ Name                   ^ Address         ^ IRQ       ^
| CPU                    | 0x00000800      | -         |
| PLL                    | 0x00000000      | -         |
| ONCHIP_MEM             | 0x00002000      | -         |
| LEDS                   | 0x00000010      | -         |
| SYSID                  | 0x00000020      | -         |
| SRAM                   | 0x00400000      | -         |
| TRISTATE_BRIDGE_0      | -               | -         |
| UCPROBE_UART           | 0x00000028      | 0         |
| JTAG_UART_0            | 0x00000030      | 1         |
| SYS_TIMER              | 0x00000040      | 2         |
| MM_CONSOLE_MASTER      | -               | -         |
| PWR_DATA               | 0x00000060      | -         |
| I2C_INT                | 0x00000080      | -         |
| PWR_EN_CLK             | 0x000000a0      | -         |
| AD7689_0               | 0x000000c0      | -         |
|  **Table 1 System components**  |||

The Nios II processor contains a peripheral that implements the communication protocol with the DUT. The peripheral is divided into three logical modules: a module which implements the interface with the Avalon bus and the communication with the SRAM, a module which implements an Avalon master interface which is used to write data directly in the SRAM and a module which communicates with the evaluation board. Following is presented a block diagram of the HDL core and a description of the interface signals.

{{ :resources:fpga:altera:ced1z:ad7689_core_pinout.png?500 |Avalon core pinout diagram}}

Table 2 describes the port definitions of the Avalon peripheral:

^ Port ^ Direction ^ Width ^ Description ^
| //**Generic pins**// ||||
| FPGA_CLK_I                | IN  | 1  | System clock. Designed with a 98MHz clock |
| RESET_I                   | IN  | 1  | System reset |
| //**Avalon Slave Interface**// ||||
| AVALON_WRITEDATA_I        | IN  | 32 | Slave write data bus |
| AVALON_WRITE_I            | IN  | 1  | Slave write data request |
| AVALON_READ_I             | IN  | 1  | Slave read data request |
| AVALON_ADDRESS_I          | IN  | 2  | Slave address bus |
| AVALON_READDATA_O         | OUT | 32 | Slave read data bus|
| //**Avalon Master Interface**// ||||
| AVALON_MASTER_WAITREQUEST | IN  | 1  | Master wait request signal |
| AVALON_MASTER_ADDRESS_O   | OUT | 32 | Master address bus |
| AVALON_MASTER_WRITE_O     | OUT | 1  | Master write signal |
| AVALON_MASTER_BYTEENABLE_O| OUT | 4  | Master byte enable signals |
| AVALON_MASTER_WRITEDATA_O | OUT | 32 | Master write data bus |
| //**External connectors**// ||||
| BDB_IO                    | IO | 16 | Bidirectional data bus used to write/read data to/from the AD7689EDZ board |
| BBUSY_I                   | IN | 1  | Signal that indicates the status of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes high |
| BRD_N_O                   | OUT | 1  | Signal used by the CED1Z board to read data from the AD7689EDZ board |
| BWR_N_O                   | OUT | 1  | Signal used by the CED1Z board to write data to the AD7689EDZ board |
| BADDR_O                   | OUT | 5  | Used to select the register to be read from the AD7689EDZ board. |
| BRESET_O                  | OUT | 1  | Used to reset the evaluation board |
|  **Table 2 Port description**  ||||

Table 3 describes the registers of the Avalon peripheral:

^ Name ^ Offset ^ Width ^ Access ^ Description ^
| CONTROL_REGISTER          | 0  | 32  | RW | Bit 0 is used to start data acquisition \\ Bit 1 is used to initiate software reset of the core \\ Bit 2 is used to configure the Avalon write master core to write data to the same location \\ Bit 3 is used to write data to the AD7689 evaluation board|
| ACQ_COUNT_REGISTER        | 1  | 32  | RW | Register used to configure the number of samples to be acquired when acquisition is started |
| BASE_REGISTER             | 2  | 32  | RW | Register used to configure the base address of the memory location where the acquired data is to be written |
| STATUS                    | 3  | 32  | R  | Bit 0 is used to signal that the acquisition is complete \\ Bit 1 is used to signal that the internal memory buffer has been overflown \\ Bit 2 is used to signal that the user has performed a write of a read only register register|
| DUT_WRITE_REGISTER        | 4  | 32  | W  | Register used to perform writes on the device under test. Bits [15:0] are used for data and [20:16] are used as address. The rest are discarded |
|  **Table 3 Register description**  |||||

The follwing figure presents the timing diagram for the read operations from the AD7689 driver .

{{ :resources:fpga:altera:ced1z:ad7689_read_timing.png?500 |Read operations time diagram}}

===== AD7689 Evaluation Board Design =====

In order to acquire data from the AD7689, several modules are implemented in the evaluation board FPGA.

{{ :resources:fpga:altera:ced1z:ad7689edz_system.png?800 | Evaluation board design overview}}

=== AD7689 module ===

This module is the actual driver of the AD7689 data acquisition system.

{{ :resources:fpga:altera:ced1z:ad7689_driver_pinout.png?400 | AD7689 driver pinout }}

^ Port ^ Direction ^ Width ^ Description ^
| //**General Connectors**// ||||
| FPGA_CLK_I                | IN  | 1  | 20 MHz clock |
| ADC_CLK_I                 | IN  | 1  | 20 MHz clock |
| RESET_I                   | IN  | 1  | Module reset |
| //**CED1Z_interface connectors**// ||||
| WR_DATA_N_I               | IN  | 1  | Signal used to write data in the driver’s internal registers, data which will be sent to the AD7689 |
| DATA_I                    | IN  | 16 | Data bus, used to send new configuration words to the AD7689 |
| DATA_CHANNELS_O           | OUT | 128| Parallel bus to transfer the data to the CED1Z_interface module |
| DATA_RD_READY_O           | OUT | 1  | Signals that at port DATA_CHANNELS_O there is new data available |
| DATA_WR_READY_O           | OUT | 1  | Signals that the write from CED1Z_interface has been performed |
| //**AD7689 connectors**// ||||
| MISO_I                    | IN  | 1  | Signal connected to the SDO pin of the AD7689 |
| MOSI_O                    | OUT | 1  | Signal connected to the DIN pin of the AD7689 |
| SCLK_O                    | OUT | 1  | Signal connected to the SCK pin of the AD7689. 20 MHz clock |
| CNV_O                     | OUT | 1  | Signal connected to the CNV pin of the AD7689 |
|  **Table 4 Port description for the AD7689 module**  ||||

=== CED1Z_interface ===

This module is used to communicate with the CED1Z board. It reads the data from the AD7689 module and forwards it to the CED1Z board. It also forwards write requests from the CED1Z board to the AD7689 module, in order to reconfigure the AD7689 acquisition system. In case the acquisition is done on 8 channels, data is mapped at addresses starting from 0x10 (channel 0) to 0x17 (channel 8). In case a single channel is acquired, data is mapped sequentially on each of the eight addresses. In this case, data must be concatenated by the module running on the CED1Z board.

=== PLL ===

This module is used to generate a 20 MHz clock signal from the 100MHz external clock signal that is available on the evaluation board.

====== Quick Evaluation ======

The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/FPGA folder.

The Evaluation Board design presented on this page is different than the default design loaded on the AD7689EDZ. In order to use the design from this page, the Evaluation Board FPGA must be reprogrammed. To reprogram the FPGA on the Evaluation board, the following steps must be followed, AFTER the CED1Z FPGA has been programmed using program_fpga.bat:
  * 1. Connect the USB-Blaster to the P2 port
  * 2. Start Quartus II, Start Tools ->Programmer
  * 3. Select Mode Active Serial Programming
  * 4. Press Add File and select EvalBoardAD7689.pof
  * 5. Check Program/Configure and Press Start.
  * 6. After the programming ends, power off the CED1Z and reprogramm it using program_fpga.bat as described above.

<WRAP round help> This is a one time operation, as the programming is done on a non volatile memory on the Evaluation Board. In order to restore the original firmware on the Evaluation Board, at step 4 use the configuration file from the CD at Evaluation Board FPGA code/uMUX FPGA CED 2-2/toplevel.pof.</WRAP>

In order to acquire data, follow the instructions in the //**Evaluation Project Data Acquisition**// section.

====== NIOS II Software Design ======

{{page>:resources:fpga:altera:ced1z:common_software_design}}

====== Evaluation Project Data Acquisition ======

After the FPGA is correctly programmed the data acquisition process can start by executing one of the three available batch scripts:
  *  1. data_capture_noseq.bat, captures data from a single channel at 250 KSPS. By editting the data_capture_noseq.tcl, the channel that is to be acquired can be changed. The resulting data is stored in Acquisition.csv.
  *  2. data_capture4diff.bat, captures data from up to 4 differential channels. By editting the data_capture4diff.tcl, the number of channels that are to be acquired can be changed. The resulting data is stored in Acquisition.csv. The sample rate is 250 KSPS divided by the number of acquired channels.
  *  3. data_capture8chan.bat, captures data from up to 8 channels, referenced to GND. By editting the data_capture8chan.tcl, the number of channels that are to be acquired can be changed.  The resulting data is stored in Acquisition.csv. The sample rate is 250 KSPS divided by the number of acquired channels.

<WRAP round help>When changing between the data capture scripts the system must be reinitialized by reprogramming the FPGA.</WRAP>

If the resulting csv file is opened with Microsoft Excel, the data will be displayed on a single column for the first script or on 8 columns for the second and third scripts. Each column represents a channel. If the AD7689 is configured to acquire less than 8 channels the remaining channels will have a constant value. For example, in the below picture, the AD7689 was configure to acquire data on 4 differential channels, a sine signal was applied on the first channel and the rest were left floating. In this case, the first column can be plotted as a sine wave, the next 3 have some noise on them, and the last 4 have a constant value of 0.

{{ :resources:fpga:altera:ced1z:4chan.png?800 | Plot of acquired data}}

====== More information ======
  * [[ez>community/fpga|ask questions about the FPGA reference design]]
  * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}
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