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resources:fpga:altera:ced1z:ad7626 [28 May 2012 16:19]
ACozma [Software Tools] 		resources:fpga:altera:ced1z:ad7626 [05 Nov 2012 17:25] (current)
AdrianC Updated the quick evaluation section with procedure on how to reprogram the Evaluation Board
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>AD7626|EVAL-AD7625_26EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]**, the Nios II Embedded Development Suite (EDS) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD7626 Evaluation Board with the CED1 board.+This document presents the steps to setup an environment for using the **[[adi>AD7626|EVAL-AD7625_26EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]** and Nios II Embedded Development Suite (EDS) . Below is presented a picture of the EVAL-AD7626 Evaluation Board with the CED1 board.
  
 {{ :resources:fpga:altera:ced1z:ced1z_ad7626.png?500 }} {{ :resources:fpga:altera:ced1z:ced1z_ad7626.png?500 }}
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   * [[adi>/static/imported-files/eval_boards/EVAL-AD7625_7626EDZ.pdf|EVAL-AD7625_26EDZ evaluation board user guide]]   * [[adi>/static/imported-files/eval_boards/EVAL-AD7625_7626EDZ.pdf|EVAL-AD7625_26EDZ evaluation board user guide]]
   * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]   * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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   * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0   * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0
   * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0   * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool 
  
 The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web.  The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. 
- 
-The **Micrium uC/Probe Trial** version is available via download from the web at [[http://micrium.com/download/Micrium-uC-Probe-Setup-Trial.exe]]. **Note:** After installation add to the “Path” system variable the entry "//%QUARTUS_ROOTDIR%\bin\//“ on the third position in the list. 
  
 ===== Downloads ===== ===== Downloads =====
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 ===== Extract the Lab Files ===== ===== Extract the Lab Files =====
  
-Create a folder called “**//ADIEvalBoard//**” on your PC and extract the **//ad7626_evalboard.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoard//** folder: **//EvalBoardFPGA//**, **//FPGA//**, **//Hdl//**, **//NiosCpu//**, **//Software//**, **//ucProbe//**+Create a folder called “**//ADIEvalBoard//**” on your PC and extract the **//ad7626_evalboard.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoard//** folder: **//EvalBoardFPGA//**, **//FPGA//**, **//Hdl//**, **//NiosCpu//**, **//Software//**, **//DataCapture//**
  
 ^ **Folder** ^ **Description** ^ ^ **Folder** ^ **Description** ^
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 | Hdl | Contains the source files for the AD7626 HDL driver: \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files.  \\ - The //tb// folder contains the sources of the core's testbench | | Hdl | Contains the source files for the AD7626 HDL driver: \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files.  \\ - The //tb// folder contains the sources of the core's testbench |
 | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the AD7626 SOPC component | | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the AD7626 SOPC component |
-| Software | Contains the source files of the uCProbe library and the main file of the Nios2 SBT evaluation project | +| Software | Contains the source files of the Nios2 SBT evaluation project | 
-| uCProbe | Contains the uCProbe interface and data capture script used to acquire data from the evaluation board and store it in a local .csv file |+| DataCapture | Contains the script files used for data acquisition |
  
 ===== Install the USB-Blaster Device Driver ===== ===== Install the USB-Blaster Device Driver =====
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 | AVALON_MASTER_WAITREQUEST | IN  | 1  | Master wait request signal | | AVALON_MASTER_WAITREQUEST | IN  | 1  | Master wait request signal |
 | AVALON_MASTER_ADDRESS_O   | OUT | 32 | Master address bus | | AVALON_MASTER_ADDRESS_O   | OUT | 32 | Master address bus |
-| AVALON_MASTER_BYTEENABLE_O| OUT | 4  | Master byte enable signals | +| AVALON_MASTER_BYTEENABLE_O| OUT | 2  | Master byte enable signals | 
-| AVALON_MASTER_WRITEDATA_O | OUT | 32 | Master write data bus |+| AVALON_MASTER_WRITEDATA_O | OUT | 16 | Master write data bus |
 | //**External connectors**// |||| | //**External connectors**// ||||
 | BDB_IO                 | I/O | 16 | Bidirectional data bus used to write/read data to/from the AD7625_26EDZ board | | BDB_IO                 | I/O | 16 | Bidirectional data bus used to write/read data to/from the AD7625_26EDZ board |
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 {{ :resources:fpga:altera:ced1z:ad7626_read_timing.png?500 |Read operations time diagram}} {{ :resources:fpga:altera:ced1z:ad7626_read_timing.png?500 |Read operations time diagram}}
  
-===== AD7626 HDL driver =====+===== AD7626 HDL driver for "Echoed-clock" mode =====
  
 In order to acquire data from the AD7626, several modules are implemented in the evaluation board FPGA. In order to acquire data from the AD7626, several modules are implemented in the evaluation board FPGA.
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 ====== Quick Evaluation ====== ====== Quick Evaluation ======
-{{page>:resources:fpga:altera:ced1z:common_quick_evaluation}} 
  
-====== NIOS II Software Design ====== +The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/FPGA folder.
-{{page>:resources:fpga:altera:ced1z:common_nios2_software_design}}+
  
-====== uC-Probe Interface ====== +The Evaluation Board design presented on this page is different than the default design loaded on the AD7626EDZ. In order to use the design from this page, the Evaluation Board FPGA must be reprogrammed. To reprogram the FPGA on the Evaluation board, the following steps must be followed, AFTER the CED1Z FPGA has been programmed using program_fpga.bat: 
-{{page>:resources:fpga:altera:ced1z:common_ucprobe}}+  * 1. Connect the USB-Blaster to the P2 port 
 +  * 2. Start Quartus II, Start Tools ->Programmer 
 +  * 3. Select Mode Active Serial Programming 
 +  * 4. Press Add File and select EvalBoardFPGA\AD7626.pof 
 +  * 5. Check Program/Configure and Press Start. 
 +  * 6. After the programming ends, power off the CED1Z and reprogramm it using program_fpga.bat as described above.
  
-===== Load and Run the Demonstration Project =====+In order to acquire data, follow the instructions in the //**Evaluation Project Data Acquisition**// section.
  
-  * Click the **//Open//** option from the **uC-Probe** menu and select the file **//ADIEvalBoard/ucProbe/AD7626_Interface.wsp//**.+====== NIOS II Software Design ====== 
 +{{page>:resources:fpga:altera:ced1z:common_software_design}}
  
-{{:resources:fpga:altera:ced1z:ucprobeopen.png?400}}{{:resources:fpga:altera:ced1z:ad7626interfaceopen.png?400}}+====== Evaluation Project Data Acquisition ======
  
-  * Before opening the interface **uC-Probe** will ask for a symbols file that must be associated with the interface. If the lab was done according to the steps provided in the **Quick Evaluation** section, select the file **//ADIEvalBoard/ucProbe/ADIEvalBoard.elf//** to be loaded as a symbol file, otherwise select the file **//ADIEvalBoard/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf//** to be loaded as a symbol file. +In order to capture data from the ADC the following steps must be performed:
- +
-{{:resources:fpga:altera:ced1z:loadelfucprobe.png?400}}{{:resources:fpga:altera:ced1z:loadelfsoftware.png?400}} +
- +
-  * Run the demonstration project by pressing the **//Play//** button. +
- +
-{{ :resources:fpga:altera:bemicro:image081.png?300 }} +
- +
-  * Run the //**ADIEvalBoard/uCProbe/data_capture.bat**// script. A DOS command prompt window will open. This window must be closed only when the uCProbe demonstration project will be closed. +
-====== Evaluation Project User Interface ====== +
- +
-The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-AD7625_26EDZ evaluation board. +
- +
-{{ :resources:fpga:altera:ced1z:ad7626interface.png?600 |Demonstration Project User Interface}} +
- +
-In order to capture data from the ADC using the uCProbe demonstration project the following steps must be performed:+
   * Make sure that the //**CED1Z FPGA**// is properly programmed and the USB Blaster is connected to the CED1Z board.   * Make sure that the //**CED1Z FPGA**// is properly programmed and the USB Blaster is connected to the CED1Z board.
-  * Start **//uc/Probe//** application. +  * Execute //**data_capture.bat**// script. At this point 1 Mbyte of data will be acquired from the ADC and saved into the CED1Z SRAM memory. The data stored in the CED1Z SRAM memory is transfered to the PC through the JTAG-UART link provided by the USB Blaster. After the data is transferred to the PC it is converted to 2's Complement 16 bit values. 
-  * Press **//Acquisition//** button. At this point 1 Mbyte of data will be acquired from the ADC and saved into the CED1Z SRAM memory. The **//Acquisition In Progress//** LED is lit to signal that the data is acquired from the ADC. When the data acquisition is complete the //**Acquisition Complete**// LED turns green. +  * The resulting data is saved into a comma separated values (.csv) file named **//Acquisition.csv//**, located in the same folder as the //**data_capture.bat**// file.
-  * The data stored in the CED1Z SRAM memory is transfered to the PC through the JTAG-UART link provided by the USB Blaster. The **//Transfer In Progress//** LED is lit as long as the data is transferred from the CED1Z to the PC. Whe the data transfer is complete the //**Transfer Complete**// LED turns green. +
-  * After the data is transferred to the PC it is converted to 2's Complement 16 bit values. The **//Processing Data In Progress//** LED is lit as long as the data conversion is performed. When the conversion is complete the //**Processing Data Complete**// LED turns green. +
-  * The data captured from the ADC is saved into a comma separated values (.csv) file named **//Acquisition.csv//**, located in the same folder as the //**data_capture.bat**// file. While the data is saved the **//Writing File In Progress//** LED is lit. When the data write process is complete the //**Writing in File Complete**// LED turns green.+
   * The data capture status is also displayed in the opened command window as shown in the figure below.   * The data capture status is also displayed in the opened command window as shown in the figure below.
  
 {{ :resources:fpga:altera:cedz:cmd_interface.png?500 |Demonstration Project Command Interface}} {{ :resources:fpga:altera:cedz:cmd_interface.png?500 |Demonstration Project Command Interface}}
-  * A new acquisition can be started by reactivating the **//Acquisition//** button. +  * A new acquisition can be started by executing the //**data_capture.bat**// script.
-  * After all the needed data is acquired the uCProbe program and the command window can be closed.+
  
 //**Note:**// If several consecutive data acquisitions are performed the captured data is appended to the **//Acquisition.csv//** file. //**Note:**// If several consecutive data acquisitions are performed the captured data is appended to the **//Acquisition.csv//** file.
  
-====== Troubleshooting ====== +====== More information ====== 
-{{page>:resources:fpga:altera:ced1z:common_troubleshooting}} +  * [[ez>community/fpga|ask questions about the FPGA reference design]] 
- +  * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}

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