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| resources:fpga:altera:bemicro:cn0187 [17 Jan 2012 14:05] – Added CN0187. Dragos Bogdan | resources:fpga:altera:bemicro:cn0187 [26 Jan 2021 01:22] (current) – update arrow links after their web site update Robin Getz | ||
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| * [[adi> | * [[adi> | ||
| - | ===== Evaluation Boards | + | ===== Reference Circuits |
| - | + | ||
| - | * [[adi> | + | |
| + | * [[adi> | ||
| ====== Overview ====== | ====== Overview ====== | ||
| - | This lab presents the steps to setup an environment for using the **[[adi> | + | This lab presents the steps to setup an environment for using the **[[adi> |
| {{ : | {{ : | ||
| - | For component evaluation and performance purposes, as opposed to quick prototyping, | + | {{page>common_sdp}} |
| - | * a controller board, like the **[[resources/ | + | |
| - | * an compatible Analog Devices SDP [[adi>sdp# | + | |
| - | * corresponding PC software | + | |
| - | The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. | + | |
| Below is presented a picture of **SDP-B** Controller Board with the **EVAL-CN0187-SDPZ** Evaluation Board. | Below is presented a picture of **SDP-B** Controller Board with the **EVAL-CN0187-SDPZ** Evaluation Board. | ||
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| - | The [[adi>AD72661]] is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 2 MSPS. The device contains two ADCs, each preceded by a 3-channel multiplexer, | + | The [[adi>AD7266]] is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 2 MSPS. The device contains two ADCs, each preceded by a 3-channel multiplexer, |
| The conversion process and data acquisition use standard control inputs allowing easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CS; conversion is also initiated at this point. The conversion time is determined by the SCLK frequency. There are no pipelined delays associated with the part. | The conversion process and data acquisition use standard control inputs allowing easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CS; conversion is also initiated at this point. The conversion time is determined by the SCLK frequency. There are no pipelined delays associated with the part. | ||
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| * [[adi> | * [[adi> | ||
| * [[adi> | * [[adi> | ||
| - | * [[adi>/ | + | * [[adi> |
| - | * [[http://www.arrownac.com/solutions/ | + | * [[https://www.intel.com/content/ |
| * [[http:// | * [[http:// | ||
| - | * [[http:// | + | * [[http:// |
| ====== Getting Started ====== | ====== Getting Started ====== | ||
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| Below is presented the list of required hardware items: | Below is presented the list of required hardware items: | ||
| - | * Arrow Electronics [[http://www.arrow.com/bemicrosdk/|BeMicro SDK]] FPGA-based MCU Evaluation Board | + | * Arrow Electronics [[https://www.intel.com/content/www/ |
| - | * [[http:// | + | * [[adi> |
| * **EVAL-CN0187-SDPZ** evaluation board | * **EVAL-CN0187-SDPZ** evaluation board | ||
| * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory | * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory | ||
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| * [[http:// | * [[http:// | ||
| * [[https:// | * [[https:// | ||
| - | * [[http:// | + | * [[http:// |
| - | * {{{{: | + | |
| The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. | The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. | ||
| - | The **Micrium uC/Probe Trial** version is available via download from the web at [[http:// | + | The **Micrium uC/Probe Trial** version |
| + | ===== Downloads ===== | ||
| + | * {{{{: | ||
| ===== Extract the Lab Files ===== | ===== Extract the Lab Files ===== | ||
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| {{page> | {{page> | ||
| - | |||
resources/fpga/altera/bemicro/cn0187.1326805534.txt.gz · Last modified: 17 Jan 2012 14:05 by Dragos Bogdan