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| resources:fpga:altera:bemicro:adn2850 [19 Sep 2011 15:51] – Images from overview section were changed. Dragos Bogdan | resources:fpga:altera:bemicro:adn2850 [26 Jan 2021 01:22] (current) – update arrow links after their web site update Robin Getz |
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| ====== ADN2850: Nonvolatile Memory, Dual 1024-Position Digital Resistor ====== | ====== BeMicro FPGA Project for ADN2850 with Nios driver ====== |
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| | ===== Supported Devices ===== |
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| | * [[adi>ADN2850]] |
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| | ===== Evaluation Boards ===== |
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| | * [[adi>EVAL-ADN2850SDZ ]] |
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| ====== Overview ====== | ====== Overview ====== |
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| This lab presents the steps to setup an environment for using the **EVAL-ADN2850SDZ** evaluation board together with the **BeMicro SDK** USB stick, the Nios II Embedded Development Suite (EDS) and the Micrium uC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-ADN2850SDZ Evaluation Board with the BeMicro SDK Platform. | This lab presents the steps to setup an environment for using the **[[adi>EVAL-ADN2850SDZ]]** evaluation board together with the **[[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]]** USB stick, the Nios II Embedded Development Suite (EDS) and the [[http://micrium.com/tools/ucprobe/overview/|Micrium μC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-ADN2850SDZ Evaluation Board with the BeMicro SDK Platform. |
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| {{ :resources:fpga:altera:bemicro:ad2850_bemicro.png?400 }} | {{ :resources:fpga:altera:bemicro:ad2850_bemicro.png?400 }} |
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| For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices System Demonstration Platform (**SDP**). The **SDP** consists of the **EVAL-SDP-CB1Z (SDP-B)** controller board, various Analog Devices component evaluation daughter boards such as the **EVAL-ADN2850SDZ** and corresponding PC software. The **EVAL-SDP-CB1Z** controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-ADN2850SDZ** Evaluation Board. | {{page>common_sdp}} |
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| | Below is presented a picture of **SDP-B** Controller Board with the **EVAL-ADN2850SDZ** Evaluation Board. |
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| {{ :resources:fpga:altera:bemicro:ad2850_sdp1z.png?400 }} | {{ :resources:fpga:altera:bemicro:ad2850_sdp1z.png?400 }} |
| The [[adi>ADN2850]] is a dual-channel, nonvolatile memory, digitally controlled resistors with 1024-step resolution, offering guaranteed maximum low resistor tolerance error of ±8%. The device performs the same electronic adjustment function as a mechanical rheostat with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. The versatile programming of the ADN2850 via an SPI®-compatible serial interface allows 16 modes of operation and adjustment including scratchpad programming, memory storing and restoring, increment/decrement, ±6 dB/step log taper adjustment, wiper setting readback, and extra EEMEM for user-defined information such as memory data for other components, look-up table, or system identification information. | The [[adi>ADN2850]] is a dual-channel, nonvolatile memory, digitally controlled resistors with 1024-step resolution, offering guaranteed maximum low resistor tolerance error of ±8%. The device performs the same electronic adjustment function as a mechanical rheostat with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. The versatile programming of the ADN2850 via an SPI®-compatible serial interface allows 16 modes of operation and adjustment including scratchpad programming, memory storing and restoring, increment/decrement, ±6 dB/step log taper adjustment, wiper setting readback, and extra EEMEM for user-defined information such as memory data for other components, look-up table, or system identification information. |
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| Complete specifications for the **ADN2850** part can be found in the datasheet available at: [[adi>ADN2850|ADN2580 Product page]]. | ===== More information ===== |
| | * [[adi>ADN2850|ADN2850 Product Info]] - pricing, samples, datasheet |
| Complete specifications for the **EVAL-ADN2850SDZ** board can be found in the [[adi>/static/imported-files/user_guides/UG-276.pdf|evaluation’s board user guide]]. | * [[adi>/static/imported-files/user_guides/UG-276.pdf|EVAL-ADN2850SDZ evaluation board user guide]] |
| | * [[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]] |
| Complete specifications for the EVAL-SDP-CB1Z board can be found in the [[adi>/static/imported-files/user_guides/UG-276.pdf/UG-277.pdf|controller board user guide]]. | * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]] |
| | * [[http://micrium.com/tools/ucprobe/overview/|Micrium uC-Probe]] |
| Complete specifications for the BeMicro SDK are available at: | |
| [[http://www.arrownac.com/solutions/bemicro-sdk]] | |
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| Complete specifications for the Nios II Embedded Development Suite (EDS) can be found at: | |
| [[http://www.altera.com/devices/processor/nios2]] | |
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| Complete specifications for the Micrium uC-Probe) can be found at: | |
| [[http://micrium.com/page/products/tools/probe]] | |
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| ====== Getting Started ====== | ====== Getting Started ====== |
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| Below is presented the list of required hardware items: | Below is presented the list of required hardware items: |
| * Arrow Electronics [[http://www.arrow.com/bemicrosdk/|BeMicro SDK]] FPGA-based MCU Evaluation Board | * Arrow Electronics [[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]] FPGA-based MCU Evaluation Board |
| * [[http://www.arrownac.com/solutions/adi_interposer/|BeMicro SDK/SDP Interposer]] adapter board | * [[adi>sdp-bemicro|BeMicro SDK/SDP Interposer]] adapter board |
| * **EVAL-ADN2850SDZ** evaluation board | * **EVAL-ADN2850SDZ** evaluation board |
| * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory | * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory |
| * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0 | * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0 |
| * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0 | * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0 |
| * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool | * [[http://micrium.com/tools/ucprobe/trial/|uC-Probe]] run-time monitoring tool, version 2.5 |
| * {{:resources:fpga:altera:bemicro:adievalboardlab.zip|Lab Design Files}} | |
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| The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. | The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. |
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| The **Micrium uC/Probe Trial** version is available via download from the web at [[http://micrium.com/download/Micrium-uC-Probe-Setup-Trial.exe]]. After installation add to the “Path” system variable the entry "//%QUARTUS_ROOTDIR%\bin\//“ on the third position in the list. | The **Micrium uC/Probe Trial** version 2.5 is available via download from the web at [[http://micrium.com/tools/ucprobe/trial/]]. After installation add to the “Path” system variable the entry "//%QUARTUS_ROOTDIR%\bin\//“ on the third position in the list. |
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| | ===== Downloads ===== |
| | * {{:resources:fpga:altera:bemicro:ad2850_evalboardlab.zip|Lab Design Files}} |
| ===== Extract the Lab Files ===== | ===== Extract the Lab Files ===== |
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| Create a folder called “**//ADIEvalBoardLab//**” on your PC and extract the **//ADIEvalBoardLab.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoardLab//** folder: **//FPGA//**, **//Software//**, **//ucProbeInterface//**, **//NiosCpu//**. | Create a folder called “**//ADIEvalBoardLab//**” on your PC and extract the **//ad2850_evalboardlab.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoardLab//** folder: **//FPGA//**, **//Software//**, **//ucProbeInterface//**, **//NiosCpu//**. |
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| {{ :resources:fpga:altera:bemicro:labfolders.png?500 }} | {{ :resources:fpga:altera:bemicro:labfolders.png?500 }} |
| {{page>common_usb}} | {{page>common_usb}} |
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| | ====== Quick Evaluation ====== |
| {{page>common_quick_eval}} | {{page>common_quick_eval}} |
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| | ====== FPGA Design ====== |
| {{page>common_spi_i2c}} | {{page>common_spi_i2c}} |
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| | ====== NIOS II Software Design ====== |
| {{page>common}} | {{page>common}} |
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| * Before opening the interface **uC-Probe** will ask for a symbols file that must be associated with the interface. If the lab was done according to the steps provided in the **Quick Evaluation** section, select the file **//ADIEvalBoardLab/ucProbeInterface/ADIEvalBoard.elf//** to be loaded as a symbol file, otherwise select the file **//ADIEvalBoardLab/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf//** to be loaded as a symbol file. | * Before opening the interface **uC-Probe** will ask for a symbols file that must be associated with the interface. If the lab was done according to the steps provided in the **Quick Evaluation** section, select the file **//ADIEvalBoardLab/ucProbeInterface/ADIEvalBoard.elf//** to be loaded as a symbol file, otherwise select the file **//ADIEvalBoardLab/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf//** to be loaded as a symbol file. |
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| {{:resources:fpga:altera:bemicro:ucprobeopenelfquickeval.png?300}} | {{:resources:fpga:altera:bemicro:ucprobeopenelfquickeval.png?400}} |
| {{:resources:fpga:altera:bemicro:ucprobeopenelfnormal.png?300}} | {{:resources:fpga:altera:bemicro:ucprobeopenelfnormal.png?400}} |
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| * Run the demonstration project by pressing the **//Play//** button. | * Run the demonstration project by pressing the **//Play//** button. |
| {{ :resources:fpga:altera:bemicro:image083.jpg?700 }} | {{ :resources:fpga:altera:bemicro:image083.jpg?700 }} |
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| **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. | **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. |
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| **Section B** is used to send commands specific for the two RDAC channels available in the ADn2850. Toggling to **//On//** the switches under a specific RDAC will send the command only to that RDAC. The following commands can be sent to the two RDAC channels individually: | **Section B** is used to send commands specific for the two RDAC channels available in the ADn2850. Toggling to **//On//** the switches under a specific RDAC will send the command only to that RDAC. The following commands can be sent to the two RDAC channels individually: |
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| | {{page>troubleshooting}} |
