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| resources:fpga:altera:bemicro:ad7980 [28 Sep 2012 09:20] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina | resources:fpga:altera:bemicro:ad7980 [12 Oct 2012 10:36] – [AD7980 Evaluation Project Overview] Andrei Cozma |
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| | ADC_CLK_I | IN | 1 | Clock to be sent to the ADC during the conversion process. | | | ADC_CLK_I | IN | 1 | Clock to be sent to the ADC during the conversion process. | |
| | //**IP control and data ports**// |||| | | //**IP control and data ports**// |||| |
| | DATA_O | OUT | 16 | Outputs the data read from the ADC. The channel ID is stored on the 4 most significant bits and the read data is stored on the 12 least significant bits. If the ADC is driven in word read mode then the channel ID will always be 0. | | | DATA_O | OUT | 16 | Outputs the data read from the ADC. | |
| | DATA_RD_READY_O | OUT | 1 | Active high signal to indicate the status of a read operation from the AD7980. The IP continuously reads the conversion results from the ADC and outputs them on the DATA_O bus. When this signal is high data can be read from the DATA_O bus. | | | DATA_RD_READY_O | OUT | 1 | Active high signal to indicate the status of a read operation from the AD7980. The IP continuously reads the conversion results from the ADC and outputs them on the DATA_O bus. When this signal is high data can be read from the DATA_O bus. | |
| | //**AD7980 control and data ports**// |||| | | //**AD7980 control and data ports**// |||| |
| | ADC_SDI | IN | 1 | ADC Serial Data Input. This pin is currently not used in the design. | | | ADC_SDI | IN | 1 | ADC Serial Data Input. This pin is currently not used in the design. | |
| | ADC_SCLK_O | OUT | 1 | ADC Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. | | | ADC_SCLK_O | OUT | 1 | ADC Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. | |
| | ADC_CNV_O | OUT | 1 | ADC Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. | | | ADC_CNVST_O | OUT | 1 | ADC Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. | |
| | **Table 2 AD7980 driver ports description** |||| | | **Table 2 AD7980 driver ports description** |||| |
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