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| resources:fpga:altera:bemicro:ad7328 [10 Jul 2012 09:41] – created Alexandru.Tofan | resources:fpga:altera:bemicro:ad7328 [26 Jan 2021 01:21] (current) – update arrow links after their web site update Robin Getz |
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| ====== Overview ====== | ====== Overview ====== |
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| This lab presents the steps to setup an environment for using the **[[adi>EVAL-AD7328SDZ]]** evaluation board together with the **[[http://www.arrownac.com/solutions/bemicro-sdk/|BeMicro SDK]]** USB stick, the Nios II Embedded Development Suite (EDS) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD7328SDZ Evaluation Board with the BeMicro SDK Platform. | This lab presents the steps to setup an environment for using the **[[adi>EVAL-AD7328SDZ]]** evaluation board together with the **[[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]]** USB stick and the Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-AD7328SDZ Evaluation Board with the BeMicro SDK Platform. |
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| {{ :resources:fpga:altera:bemicro:ad7328_bemicro.jpg?400 }} | {{ :resources:fpga:altera:bemicro:ad7328_bemicro.jpg?400 }} |
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| For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: | {{page>common_sdp}} |
| * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)** | |
| * an compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]] | |
| * corresponding PC software | |
| The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ. | |
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| Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7328SDZ** Evaluation Board. | Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7328SDZ** Evaluation Board. |
| ===== More information ===== | ===== More information ===== |
| * [[adi>AD7328|AD7328 Product Info]] - pricing, samples, datasheet | * [[adi>AD7328|AD7328 Product Info]] - pricing, samples, datasheet |
| * {{:resources:fpga:altera:bemicro:user_guide_eval_10lead_pulsar.pdf|EVAL-AD7328SDZ evaluation board user guide}} | * EVAL-AD7328SDZ evaluation board user guide |
| * [[http://www.arrownac.com/solutions/bemicro-sdk|BeMicro SDK]] | * [[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]] |
| * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]] | * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]] |
| * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]] | |
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| ====== Getting Started ====== | ====== Getting Started ====== |
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| Below is presented the list of required hardware items: | Below is presented the list of required hardware items: |
| * Arrow Electronics [[http://www.arrow.com/bemicrosdk/|BeMicro SDK]] FPGA-based MCU Evaluation Board | * Arrow Electronics [[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]] FPGA-based MCU Evaluation Board |
| * [[http://www.arrownac.com/solutions/adi_interposer/|BeMicro SDK/SDP Interposer]] adapter board | * [[adi>sdp-bemicro|BeMicro SDK/SDP Interposer]] adapter board |
| * **EVAL-AD7328SDZ** evaluation board | * **EVAL-AD7328SDZ** evaluation board |
| * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory | * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory |
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| Below is presented the list of required software tools: | Below is presented the list of required software tools: |
| * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0 | * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v12.0sp2 |
| * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0 | * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v12.0sp2 |
| * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool | |
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| The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. | The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. |
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| The **Micrium uC/Probe Trial** version is available via download from the web at [[http://micrium.com/download/Micrium-uC-Probe-Setup-Trial.exe]]. After installation add to the “Path” system variable the entry "//%QUARTUS_ROOTDIR%\bin\//“ on the third position in the list. | |
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| ===== Downloads ===== | ===== Downloads ===== |
| ===== Extract the Lab Files ===== | ===== Extract the Lab Files ===== |
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| Create a folder called “**//ADIEvalBoardLab//**” on your PC and extract the **//ad7328_evalboardlab.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoardLab//** folder: **//FPGA//**, **//Hdl//** **//Software//**, **//ucProbeInterface//**, **//NiosCpu//**. | Create a folder called “**//ADIEvalBoardLab//**” on your PC and extract the **//ad7328_evalboardlab.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoardLab//** folder: **//FPGA//**, **//Hdl//** **//Software//**, **//DataCapture//**, **//NiosCpu//**. |
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| ^ **Folder** ^ **Description** ^ | ^ **Folder** ^ **Description** ^ |
| | Hdl | Contains the source files for the AD7328 HDL driver: \\ - The //doc// subfolder contains a brief documentation for the driver. \\ - The //src// subfolder contains the HDL source files. \\ - The //tb// folder contains the sources of the driver's testbench. | | | Hdl | Contains the source files for the AD7328 HDL driver: \\ - The //doc// subfolder contains a brief documentation for the driver. \\ - The //src// subfolder contains the HDL source files. \\ - The //tb// folder contains the sources of the driver's testbench. | |
| | NiosCpu | Contains the Quartus evaluation project source files . The //ip// subfolder contains the AD7328 Nios2 peripheral source code. | | | NiosCpu | Contains the Quartus evaluation project source files . The //ip// subfolder contains the AD7328 Nios2 peripheral source code. | |
| | Software | Contains the source files of the uCProbe library and the main file of the Nios2 SBT evaluation project.| | | Software | Contains the source files of the Nios2 SBT evaluation project.| |
| | uCProbeInterface | Contains the uCProbe interface and //data_capture.bat// script used to acquire data from the evaluation board and store it in a local .csv file. | | | DataCapture | Contains the script files used for data acquisition | |
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| ====== ====== | ====== ====== |
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| {{page>common_usb}} | {{page>common_usb}} |
| | TIMER | 0x00000060 | 3 | | | TIMER | 0x00000060 | 3 | |
| | AVALON MASTER | - | - | | | AVALON MASTER | - | - | |
| | Main PLL | 0x00000000 | - | | | Main PLL | 0x00000080 | - | |
| | AD7328 PERIPHERAL | 0x00000120 | - | | | AD7328 PERIPHERAL | 0x00000120 | - | |
| | **Table 1 System components** ||| | | **Table 1 System components** ||| |
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| The Nios II processor contains a peripheral that implements the communication protocol with the DUT. The peripheral is divided into three logical modules: a module which implements the interface with the Avalon bus and the communication with the onchip RAM, a module which implements an Avalon master interface which is used to write data directly in the onchip RAM and a module which is the actual driver of the DUT. The driver can also be used as standalone in FPGA designs which do not contain a softcore. Following is presented a block diagram of the HDL driver and a description of the driver's interface signals. | The Nios II processor contains a peripheral that implements the communication protocol with the DUT. The peripheral is divided into three logical modules: a module which implements the interface with the Avalon bus and the communication with the onchip RAM, a module which implements an Avalon master interface which is used to write data directly in the onchip RAM and a module which is the actual driver of the DUT. The driver can also be used as standalone in FPGA designs which do not contain a softcore. Following is presented a block diagram of the HDL driver and a description of the driver's interface signals. |
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| {{ :resources:fpga:altera:bemicro:ad7328_block_diagram.png?400 |HDL driver block diagram}} | |
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| Table 2 describes the ports of the AD7328 HDL driver. | Table 2 describes the ports of the AD7328 HDL driver. |
| | RESET_I | IN | 1 | Active low reset signal. | | | RESET_I | IN | 1 | Active low reset signal. | |
| | ADC_CLK_I | IN | 1 | Clock to be sent to the ADC during the conversion process. | | | ADC_CLK_I | IN | 1 | Clock to be sent to the ADC during the conversion process. | |
| | | DATA_I | IN | 16 | Bus for writing data to the AD7328. | |
| | //**IP control and data ports**// |||| | | //**IP control and data ports**// |||| |
| | | WR_DATA_N_I | IN | 1 | Indicates that new data is available on DATA_I bus.| |
| | DATA_O | OUT | 16 | Outputs the data read from the ADC.| | | DATA_O | OUT | 16 | Outputs the data read from the ADC.| |
| | | DATA_WR_READY_O | OUT | 1 | Active high signal to indicate the status of a write operation to AD7328.| |
| | DATA_RD_READY_O | OUT | 1 | Active high signal to indicate the status of a read operation from the AD7328. The IP continuously reads the conversion results from the ADC and outputs them on the DATA_O bus. When this signal is high data can be read from the DATA_O bus. | | | DATA_RD_READY_O | OUT | 1 | Active high signal to indicate the status of a read operation from the AD7328. The IP continuously reads the conversion results from the ADC and outputs them on the DATA_O bus. When this signal is high data can be read from the DATA_O bus. | |
| | //**AD7328 control and data ports**// |||| | | //**AD7328 control and data ports**// |||| |
| | ADC_SDO | IN | 1 | ADC Serial Data Output. The conversion result is output on this pin. It is synchronized to SCLK | | | ADC_SDO | IN | 1 | ADC Serial Data Output. The conversion result is output on this pin. It is synchronized to SCLK | |
| | ADC_SDI | OUT | 1 | ADC Serial Data Input. This pin is currently not used in the design. | | | ADC_SDI | OUT | 1 | ADC Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of the SCLK. | |
| | ADC_SCLK_O | OUT | 1 | ADC Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. | | | ADC_SCLK_O | OUT | 1 | ADC Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. | |
| | ADC_CNVST_O | OUT | 1 | ADC Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. | | | ADC_CNVST_O | OUT | 1 | ADC Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. | |
| | **Table 2 AD7328 driver ports description** |||| | | **Table 2 AD7328 driver ports description** |||| |
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| The follwing figure presents the timing diagram for the read operations from the AD7328 driver. | |
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| {{ :resources:fpga:altera:ced1z:read_timing.png?500 |Read operations time diagram}} | |
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| Table 3 describes the ports of the Avalon peripheral: | Table 3 describes the ports of the Avalon peripheral: |
| | //**External connectors**// |||| | | //**External connectors**// |||| |
| | ADC_SDO | IN | 1 | ADC Serial Data Output. The conversion result is output on this pin. It is synchronized to SCLK | | | ADC_SDO | IN | 1 | ADC Serial Data Output. The conversion result is output on this pin. It is synchronized to SCLK | |
| | ADC_SDI | IN | 1 | ADC Serial Data Input. This pin is currently not used in the design. | | | ADC_SDI | OUT | 1 | ADC Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of the SCLK. | |
| | ADC_SCLK_O | OUT | 1 | ADC Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. | | | ADC_SCLK_O | OUT | 1 | ADC Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. | |
| | ADC_CNVST_O | OUT | 1 | ADC Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. | | | ADC_CNVST_O | OUT | 1 | ADC Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. | |
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| ====== Quick Evaluation ====== | ====== Quick Evaluation ====== |
| {{page>common_quick_eval}} | {{page>common_quick_evaluation}} |
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| ====== NIOS II Software Design ====== | ====== NIOS II Software Design ====== |
| {{page>common}} | {{page>common_software_design}} |
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| ====== uC-Probe Interface ====== | |
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| A notable challenge in embedded systems development is to overcome the lack of feedback that such systems typically provide. Many developers resort to blinking LEDs or instrumenting their code with //printf()// in order to determine whether or not their systems are running as expected. **Micrium** provides a unique tool named **µC-Probe** to assist these developers. With this tool, developers can effortlessly read and write the variables on a running embedded system. | |
| This section presents the steps required to install the **Micrium uC-Probe** software tool and to run the demonstration project for the ADI evaluation board. A description of the **uC-Probe** demonstration interface is provided. | |
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| ===== Configure uC-Probe ===== | |
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| Launch **uC-Probe** from the **//Start -> All Programs -> Micrium -> uC-Probe//**. | |
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| Select **uC-Probe** options. | |
| * Click on the **uC-Probe** icon on the top left portion of the screen. | |
| * Click on the **//Options//** button to open the dialog box. | |
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| {{ :resources:fpga:altera:bemicro:ucprobeoptionsbtn.png?300 }} | |
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| Set target board communication protocol as **//JTAG UART//** | |
| * Click on the **//Communication//** tab icon on the top left portion of the dialog box | |
| * Select the **//JTAG UART//** option. | |
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| {{ :resources:fpga:altera:bemicro:image067.png?400 }} | |
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| Setup **//JTAG UART//** communication settings | |
| * Select the **//JTAG-UART//** option from the **//Communication//** tab. | |
| * Press the **//Open File//** button to select the JTAG Debug Information file (**//.jdi//**) | |
| * Navigate to the **//ADIEvalBoardLab/FPGA//** folder and select the BeMicroSDK.jdi file. Press Open. | |
| * Type the value **//1//** in the the **//Device Id//** window. | |
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| {{ :resources:fpga:altera:bemicro:ucprobeoptionsjtag.png?400 }} | |
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| * Select **//uCProbe_uart(0)//** from the **//Instance Id//** pulldown menu. | |
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| {{ :resources:fpga:altera:bemicro:image073.png?400 }} | |
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| * Press **//Apply//** and **//OK//** to exit the options menu. The embedded target has two UARTs. **uC-Probe** will be communicating with the **//uCProbe_uart//**. | |
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| ===== Load and Run the Demonstration Project ===== | |
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| * Click the **//Open//** option from the **uC-Probe** menu and select the file **//ADIEvalBoardLab/ucProbeInterface/AD7328_Interface.wsp//**. | |
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| {{:resources:fpga:altera:bemicro:ucprobeopenfile.png?400}} | |
| {{:resources:fpga:altera:bemicro:ad7328interfaceopen.png?400}} | |
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| * Before opening the interface **uC-Probe** will ask for a symbols file that must be associated with the interface. If the lab was done according to the steps provided in the **Quick Evaluation** section, select the file **//ADIEvalBoardLab/ucProbeInterface/ADIEvalBoard.elf//** to be loaded as a symbol file, otherwise select the file **//ADIEvalBoardLab/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf//** to be loaded as a symbol file. | |
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| {{:resources:fpga:altera:bemicro:ucprobeopenelfquickeval.png?400}}{{:resources:fpga:altera:bemicro:ucprobeopenelfnormal.png?400}} | |
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| * Run the demonstration project by pressing the **//Play//** button. | |
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| {{ :resources:fpga:altera:bemicro:image081.png?400 }} | |
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| * Run the //**ADIEvalBoard/uCProbe/data_capture.bat**// script. A DOS command prompt window will open. This window must be closed only when the uCProbe demonstration project will be closed. | |
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| ====== Demonstration Project User Interface ====== | ====== Demonstration Project User Interface ====== |
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| The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD7328SDZ** evaluation board. | * Execute **//data_capture.bat//** script. At this point 16 Kbyte of data will be acquired from the ADC and saved into the BeMicro SDK memory. The data stored in the BeMicro SDK memory is transfered to the PC. After the data is transferred to the PC it is converted to 12 bit plus sign values. |
| | * The data captured from the ADC is saved into a comma separated values (.csv) file named **//Acquisition.csv//**, located in the same folder as the //**data_capture.bat**// file. |
| {{ :resources:fpga:altera:bemicro:ad7328_interface.png?500 }} | |
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| In order to capture data from the ADC using the uCProbe demonstration project the following steps must be performed: | |
| * Press **//Acquisition//** button. At this point 16 Kbyte of data will be acquired from the ADC and saved into the BeMicro SDK memory. The **//Acquisition In Progress//** LED is lit to signal that the data is acquired from the ADC. When the data acquisition is complete the //**Acquisition Complete**// LED turns green. | |
| * The data stored in the BeMicro SDK memory is transfered to the PC, on a byte by byte basis. The **//Transfer In Progress//** LED is lit as long as the data is transferred from the BeMicro SDK to the PC. When the data transfer is complete the //**Transfer Complete**// LED turns green. | |
| * The **//Processing Data In Progress//** LED is lit as long as the data conversion to 16 bit values is performed. When the conversion is complete the //**Processing Data Complete**// LED turns green. | |
| * The data captured from the ADC is saved into a comma separated values (.csv) file named **//Acquisition.csv//**, located in the same folder as the //**data_capture.bat**// file. While the data is saved the **//Writing File In Progress//** LED is lit. When the data write process is complete the //**Writing in File Complete**// LED turns green. | |
| * The data capture status is also displayed in the opened command window as shown in the figure below. | * The data capture status is also displayed in the opened command window as shown in the figure below. |
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| {{ :resources:fpga:altera:bemicro:cmd_interface.png?500 |Demonstration Project Command Interface}} | {{ :resources:fpga:altera:bemicro:cmd_interface.png?500 |Demonstration Project Command Interface}} |
| * A new acquisition can be started by reactivating the **//Acquisition//** button. | * A new acquisition can be started by executing the //**data_capture.bat**// script. |
| * After all the needed data is acquired the uCProbe program and the command window can be closed. | |
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| //**Note:**// If several consecutive data acquisitions are performed the captured data is appended to the **//Acquisition.csv//** file. | //**Note:**// If several consecutive data acquisitions are performed the captured data is appended to the **//Acquisition.csv//** file. |
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| {{page>troubleshooting}} | ====== Troubleshooting ====== |
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| | {{page>troubleshooting12}} |
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| | ====== More information ====== |
| | * [[ez>community/fpga|ask questions about the FPGA reference design]] |
| | * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}} |
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