This version is outdated by a newer approved version.
This version (26 May 2015 15:30) is a draft.
Approvals: 0/1
This version (26 May 2015 15:30) is a draft.Approvals: 0/1
This is an old revision of the document!
Table of Contents
EVAL-CN0363-PMDZ HDL Reference Design
Functional Overview
The EVAL-CN0363-PMDZ HDL reference design is based on the Analog Devices base reference design for the ZED board. In addition to the base reference design EVAL-CN0363-PMDZ HDL reference design implements function blocks to communicate over a SPI bus with the AD7173 ADC to configure it and receive the raw ADC data as well a configure the AD5201 digital potentiometer. The data received from the ADC is passed to a processing pipeline which performs a digital synchronous detector and finally write the data to system memory using a DMA. The HDL reference design is also responsible for generating the LED excitation signal. A simplified functional block diagram of the system is given below.
Supported Devices
Supported Carriers
Source
FPGA Reference Designs on GitHub :
Vivado Downloads
- Main repository with latest changes (always synced with the latest release)
- Releases (the used tool version can be found in README.md)
Base reference design
The EVAL-CN0363-PMDZ HDL reference design is built on-top the standard Analog Devices base HDL reference design for the ZED board. The base reference design implements basic input and output connectivity to the ZED board, like USB, HDMI-out and audio support. It also instantiated the Xilinx PS7 processing system which contains a dual core ARM A9 applications processor which is used for running software corresponding to the reference design.
SPI communication
To implement the SPI communication logic for the EVAL-CN0363-PMDZ HDL reference design the SPI Engine framework is used. This allows the flexibility to access all configuration registers for both connected SPI devices dynamically from software as well as allowing low-latency and high-throughput automated access to the SPI bus when capturing sample data from the ADC.
The SPI-Engine AXI core in the design is mapped into the system's peripheral memory bus via a AXI-Lite bus and be accessed by the CPU. It's interrupt signal is also connected to the processing system. The SPI-Engine AXI core controls the renaming part of the SPI-Engine cores used in the design and it has primarily two functions. One is to give direct access to the SPI bus which is used to configure the configuration registers of the SPI devices. The other is to configure and control the SPI-Engine offload core.
The SPI-Engine interconnect core is used to give both the SPI-Engine AXI and SPI-Engine offload core access to the SPI-Engine execution core. The SPI-Engine offload core is connected to the first interconnect slave port, which means it has priority over the SPI-Engine AXI core. This is done because reading the ADC result data is timing critical while changing the configuration registers is typically not.
The SPI-Engine offload core is used to read the ADC result data and feeds the received data into the processing pipeline. Software is responsible for setting up the core with the correct SPI message to read the ADC result register as well as enable the core when the ADC converter is active. Once the core has been set up and enabled the stored SPI message will be executed when the data ready (RDY) signal from the ADC is detected.
The SPI-Engine execution core is responsible for handling the low level SPI bus access. It accepts the SPI-Engine commands from the SPI-Engine AXI and SPI-Engine offload core and handles them accordingly.
The SigmaDelta SPI core is responsible for monitoring the low-level SPI bus and extracting the data ready from the bus which is multiplexed over the same physical wire as the SPI MISO signal. The data ready signal is connected to the SPI-Engine offload core which starts to read the ADC conversion result when the signal is asserted. It is also connected to the processing pipeline which takes a snapshot of the current phase of the excitation signal when the data ready signal is asserted. This allows precise time-stamping of the excitation signal phase in relation to the time when the ADC conversion was performed.
Synchronous detector processing pipeline
More Information
resources/eval/user-guides/eval-cn0363-pmdz/reference_hdl.1432647029.txt.gz · Last modified: 26 May 2015 15:30 (external edit)