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resources:eval:user-guides:ad-fmcomms1-ebz:hardware:functional_overview [14 Dec 2012 17:36] – remove under construction Lars-Peter Clausenresources:eval:user-guides:ad-fmcomms1-ebz:hardware:functional_overview [09 Feb 2021 16:06] (current) – add retired Robin Getz
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 ====== AD-FMCOMMS1-EBZ Functional Overview ====== ====== AD-FMCOMMS1-EBZ Functional Overview ======
 +{{page>/wiki/common#retired&nofooter&noheader}}
 A functional block diagram of the system is given below. The system consists of four functional partitions - transmit path, receive path, clocking and power supply. A functional block diagram of the system is given below. The system consists of four functional partitions - transmit path, receive path, clocking and power supply.
  
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 | [[adi>ADL5602]] | 50 MHz to 4.0 GHz RF/IF Gain (20dB) Block. | | [[adi>ADL5602]] | 50 MHz to 4.0 GHz RF/IF Gain (20dB) Block. |
  
-In the transmit direction, the system converts complex I and Q signals to a corresponding RF signal. The [[adi>AD9122]] DAC interpolates the data and applies a frequency translation to the baseband. The complex IF shifts the fundamental signal away from DC where LO feed-through and images can be easily filtered and otherwise mitigated. This complex analog output from the DAC feeds an [[adi>ADL5375]] quadrature modulator via an appropriate filter and matching stage where it is translated to the specified RF output frequency. This signal is then passed through an image rejection filter to an [[adi>ADL5602]] for +20dB gain. The RF output power control is accomplished by adjusting the baseband data, RF outputs up to 4GHz can be synthesized in the transmit direction at power levels up to 7.5dBm.+In the transmit direction, the system converts complex I and Q signals to a corresponding RF signal. The [[adi>AD9122]] DAC interpolates the data and applies a frequency translation to the baseband. The complex baseband shifts the fundamental signal away from DC where LO feed-through and images can be easily filtered and otherwise mitigated. This complex analog output from the DAC feeds an [[adi>ADL5375]] quadrature modulator via an appropriate filter and matching stage where it is translated to the specified RF output frequency. This signal is then passed through an image rejection filter to an [[adi>ADL5602]] for +20dB gain. The RF output power control is accomplished by adjusting the baseband data, RF outputs up to 4GHz can be synthesized in the transmit direction at power levels up to 7.5dBm.
  
 The reference design generates the signals for AD9122 either from an internal DDS or external memory (via VDMA). The internal DDS consists of four independent signal generators with programmable phase offset and frequency. These four signal generators are paired to create two tones that are interleaved and driven to the DAC. The reference design generates the signals for AD9122 either from an internal DDS or external memory (via VDMA). The internal DDS consists of four independent signal generators with programmable phase offset and frequency. These four signal generators are paired to create two tones that are interleaved and driven to the DAC.
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 | [[adi>ADF4351]] | Wideband Synthesizer with Integrated VCO (35MHz to 4400MHz). | | [[adi>ADF4351]] | Wideband Synthesizer with Integrated VCO (35MHz to 4400MHz). |
  
-In the receive direction, the system converts a RF signal into complex I and Q signals. The RF signal is demodulated by the [[adi>ADL5380]] to a suitable complex IF (50MHz to 200MHz). The I and Q IF signal is filtered and then passed to the [[adi>AD8366]] DVGA, which provides upto 15.75dB of gain. An anti-alias filter is used to remove harmonics and other out of band signals before the signal is digitized with the [[adi>AD9643]].+In the receive direction, the system converts a RF signal into complex I and Q signals. The RF signal is demodulated by the direct-conversion [[adi>ADL5380]] Quadrature demodulator to a suitable complex baseband (DC to 400MHz (-3dB point)).
  
-The reference design transfers the received data to DDR via DMA. An optional off-line FFT core may be used to generate a spectrum plot.+{{:resources:eval:user-guides:ad-fmcomms1-ebz:hardware:adl5380_lowrange_basebandrespose.png?direct&400|RF = 400 MHz to 3 GHz, Normalized IQ Baseband Frequency Response}}
  
 +The resulting I and Q baseband signals are filtered and then passed to the [[adi>AD8366]] DVGA, which provides up between 4.5 dB to 20.25 dB of gain. An anti-alias filter is used to remove harmonics and other out of band signals before the signal is digitized with the [[adi>AD9643]].
 +
 +The reference design transfers the received data to DDR via DMA. An optional off-line FFT core may be used to generate a spectrum plot.
 ===== Clocking ===== ===== Clocking =====
  
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   * This is cleaned up (from a jitter standpoint) and sent to the AD9523.   * This is cleaned up (from a jitter standpoint) and sent to the AD9523.
   * The AD9523 takes this, and creates:   * The AD9523 takes this, and creates:
-    * 983.04 MHz for the DAC sample rate+    * 491.52 MHz for the DAC sample rate
     * 245.76 MHz for the ADC sample rate     * 245.76 MHz for the ADC sample rate
-    * 30.72 MHz for the reference clocks for the LO PLLs.+    * 122.88 MHz for the reference clocks for the LO PLLs.
  
 These clocks can be changed, but the key thing to remember is that the AD9523 drives both the ADC and DAC. The AD9523 has two clock banks (see figure 1 in the datasheet), Bank 0: 0-3 & 10-13, and Bank 1: 4-9. The outputs on the different banks need to be integer mutliples of eachother. The best thing to do if you are interested in the details of this, is to get the [[adi>EVAL-AD9523-1|Eval board software]], and play with the different settings (you don't need a demo board connected to run the software). These clocks can be changed, but the key thing to remember is that the AD9523 drives both the ADC and DAC. The AD9523 has two clock banks (see figure 1 in the datasheet), Bank 0: 0-3 & 10-13, and Bank 1: 4-9. The outputs on the different banks need to be integer mutliples of eachother. The best thing to do if you are interested in the details of this, is to get the [[adi>EVAL-AD9523-1|Eval board software]], and play with the different settings (you don't need a demo board connected to run the software).
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 | [[adi>ADP2323]] | Dual 3A, 20V step-down switcher. | | [[adi>ADP2323]] | Dual 3A, 20V step-down switcher. |
 | [[adi>ADP7104]] | High accuracy, 500mA LDO | | [[adi>ADP7104]] | High accuracy, 500mA LDO |
-| [[adi>ADP150/1]] | Ultra low noise, 150/200 mA LDO |+| [[adi>ADP151]] | Ultra low noise, 150/200 mA LDO |
 | [[adi>ADP1740]] | Low VIN, 2A LDO | | [[adi>ADP1740]] | Low VIN, 2A LDO |
  
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 To increase receive sensitivity, the receive path may be driven by an optional off board [[adi>ADL5523]], which is a 400 MHz to 4000 MHz Low Noise GaAs pHEMT Amplifier. This provides high gain and low noise figure for single-down conversion IF sampling receiver architectures as well as direct-down conversion receivers. To increase receive sensitivity, the receive path may be driven by an optional off board [[adi>ADL5523]], which is a 400 MHz to 4000 MHz Low Noise GaAs pHEMT Amplifier. This provides high gain and low noise figure for single-down conversion IF sampling receiver architectures as well as direct-down conversion receivers.
  
-{{ :resources:fpga:xilinx:fmc:ad-fmcomms1-ebz:xcomm_block.png?600 |}}+{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:block_diagram.png?600 |}}
  
-{{navigation AD-FMCOMMS1-EBZ#none#.:|Hardware#Card specifications}}+{{navigation AD-FMCOMMS1-EBZ#none#.:|AD-FMCOMMS1-EBZ#Card Specification}}
resources/eval/user-guides/ad-fmcomms1-ebz/hardware/functional_overview.1355502965.txt.gz · Last modified: 14 Dec 2012 17:36 by Lars-Peter Clausen

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