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resources:eval:dpg:dpg3 [17 Aug 2012 15:30]
JasonC [Hardware Specifications] 		resources:eval:dpg:dpg3 [19 Apr 2013 14:08] (current)
JasonC Added trigger threshold levels
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 {{ :resources:eval:dpg:dpg3-016.png?nolink&200 |}} {{ :resources:eval:dpg:dpg3-016.png?nolink&200 |}}
 +
 +====== Ordering Code ======
 +
 +The part number for the DPG3 is AD-DPG3.
 +
 +To request a quote, please fill out a [[https://form.analog.com/Form_Pages/support/DPGPricingRequestForm.aspx|Quote Request]]
 +
  
 ====== Hardware Specifications ====== ====== Hardware Specifications ======
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       * Up to 1.6Gbps per bit (800MHz DDR)       * Up to 1.6Gbps per bit (800MHz DDR)
       * Same connector and pinout as [[resources:eval:dpg:dpg2|DPG2]]       * Same connector and pinout as [[resources:eval:dpg:dpg2|DPG2]]
-    * High-Speed Serial Interface+    * High-Speed Serial Interface //(For JESD204 Converters)//
       * 16 Tx lanes       * 16 Tx lanes
-      * 16 Rx lanes 
       * Up to 8.5Gbps per lane       * Up to 8.5Gbps per lane
   * Memory   * Memory
Line 55: Line 61:
 ===== Input Trigger ===== ===== Input Trigger =====
 When set as an input, the unit will start playback when the trigger is asserted (raised from low to high). When set as an input, the unit will start playback when the trigger is asserted (raised from low to high).
 +
 +The input high threshold is 2.0V, and the input low threshold is 0.8V, allowing it to be directly interfaced with 3.3V logic signals.
 ===== Output Trigger ===== ===== Output Trigger =====
 When set as an output, the trigger will pulse when the playback is running at the beginning of the vector. Therefore, it will pulse every time the vector is looped when in Loop mode, or only once if the unit is in Count mode. When set as an output, the trigger will pulse when the playback is running at the beginning of the vector. Therefore, it will pulse every time the vector is looped when in Loop mode, or only once if the unit is in Count mode.
Line 60: Line 68:
 With the appropriate external synchronization board and cables, up to four DPG3's can be synchronized together when in LVDS mode. One unit is designated as the master, and all units use the master's clock instead of their own. The data will then being playback from each unit on the same clock edge. With the appropriate external synchronization board and cables, up to four DPG3's can be synchronized together when in LVDS mode. One unit is designated as the master, and all units use the master's clock instead of their own. The data will then being playback from each unit on the same clock edge.
  
-<note important>Synchronizing multiple DPGs together does //not// guarantee that the analog waveforms coming out of the attached DAC evaluation board are synchronized. Each particular DAC may require additional synchronization circuitry to ensure that the analog outputs are synchronized.</note>+<WRAP important>Synchronizing multiple DPGs together does //not// guarantee that the analog waveforms coming out of the attached DAC evaluation board are synchronized. Each particular DAC may require additional synchronization circuitry to ensure that the analog outputs are synchronized.</WRAP>
  
 //Note that the synchronization board and cables used with the DPG2 are not compatible with the DPG3// //Note that the synchronization board and cables used with the DPG2 are not compatible with the DPG3//
 +
 +<fs larger>**Multi-Unit Synchronization is not currently supported on the DPG3, but will be enabled by a future software update.**</fs>
 ====== Connector Pinouts ====== ====== Connector Pinouts ======
 The DGP3 has two separate connector systems for interfacing with evaluation boards. One, for CMOS and LVDS interface DACs, is backwards compatible with the [[resources:eval:dpg:dpg2|DPG2]]. The second connector is new to the DPG3, and supports high-speed serial, power, and communications. The DGP3 has two separate connector systems for interfacing with evaluation boards. One, for CMOS and LVDS interface DACs, is backwards compatible with the [[resources:eval:dpg:dpg2|DPG2]]. The second connector is new to the DPG3, and supports high-speed serial, power, and communications.
Line 87: Line 97:
 | O1 | GROUND | Digital Ground | | O1 | GROUND | Digital Ground |
 | A2 | GPIO3 | General-Purpose I/O 3 | | A2 | GPIO3 | General-Purpose I/O 3 |
-| B2 | GPIO2 | General-Purpose I/O 2 | +| B2 | PWR_SENSE| Pulled up to 3.3V on the evaluation board to allow the DPG3 to detect when a board is powered | 
-| C2 | GPIO1 | General-Purpose I/O 1 |+| C2 | BRD_DETECT| Tied to ground on the evaluation board to allow the DPG3 to detect a connected board |
 | D2 | GROUND | Digital Ground | | D2 | GROUND | Digital Ground |
-| E2 | RX13_N | Receive SERDES Lane (into FPGA) 13 | +| E2 | RX13_N | Receive SERDES Lane (into FPGA) 13* | 
-| F2 | RX13_P | Receive SERDES Lane (into FPGA) 13 |+| F2 | RX13_P | Receive SERDES Lane (into FPGA) 13* |
 | G2 | GROUND  | Digital Ground | | G2 | GROUND  | Digital Ground |
 | H2 | TX9_N | Transmit SERDES Lane (from FPGA) 9 | | H2 | TX9_N | Transmit SERDES Lane (from FPGA) 9 |
 | I2 | TX9_P | Transmit SERDES Lane (from FPGA) 9 | | I2 | TX9_P | Transmit SERDES Lane (from FPGA) 9 |
 | J2 | GROUND | Digital Ground  | | J2 | GROUND | Digital Ground  |
-| K2 | RX5_N | Receive SERDES Lane (into FPGA) 5 | +| K2 | RX5_N | Receive SERDES Lane (into FPGA) 5* | 
-| L2 | RX5_P | Receive SERDES Lane (into FPGA) 5 |+| L2 | RX5_P | Receive SERDES Lane (into FPGA) 5* |
 | M2 | GROUND | Digital Ground  | | M2 | GROUND | Digital Ground  |
 | N2 | TX1_N | Transmit SERDES Lane (from FPGA) 1 | | N2 | TX1_N | Transmit SERDES Lane (from FPGA) 1 |
Line 104: Line 114:
 | B3 | +6V0 | +6V Power| | B3 | +6V0 | +6V Power|
 | C3 | GROUND | Digital Ground | | C3 | GROUND | Digital Ground |
-| D3 | RX14_N | Receive SERDES Lane (into FPGA) 14 | +| D3 | RX14_N | Receive SERDES Lane (into FPGA) 14* | 
-| E3 | RX14_P | Receive SERDES Lane (into FPGA) 14 |+| E3 | RX14_P | Receive SERDES Lane (into FPGA) 14* |
 | F3 | GROUND | Digital Ground | | F3 | GROUND | Digital Ground |
 | G3 | TX10_N | Transmit SERDES Lane (from FPGA) 10 | | G3 | TX10_N | Transmit SERDES Lane (from FPGA) 10 |
 | H3 | TX10_P | Transmit SERDES Lane (from FPGA) 10 | | H3 | TX10_P | Transmit SERDES Lane (from FPGA) 10 |
 | I3 | GROUND | Digital Ground | | I3 | GROUND | Digital Ground |
-| J3 | RX6_N | Receive SERDES Lane (into FPGA) 6 | +| J3 | RX6_N | Receive SERDES Lane (into FPGA) 6* | 
-| K3 | RX6_P | Receive SERDES Lane (into FPGA) 6 |+| K3 | RX6_P | Receive SERDES Lane (into FPGA) 6* |
 | L3 | GROUND | Digital Ground | | L3 | GROUND | Digital Ground |
 | M3 | TX2_N | Transmit SERDES Lane (from FPGA) 2 | | M3 | TX2_N | Transmit SERDES Lane (from FPGA) 2 |
Line 120: Line 130:
 | C4 | +6V0 | +6V Power | | C4 | +6V0 | +6V Power |
 | D4 | GROUND | Digital Ground | | D4 | GROUND | Digital Ground |
-| E4 | RX15_N | Receive SERDES Lane (into FPGA) 15 | +| E4 | RX15_N | Receive SERDES Lane (into FPGA) 15* | 
-| F4 | RX15_P | Receive SERDES Lane (into FPGA) 15 |+| F4 | RX15_P | Receive SERDES Lane (into FPGA) 15* |
 | G4 | GROUND  | Digital Ground | | G4 | GROUND  | Digital Ground |
 | H4 | TX11_N | Transmit SERDES Lane (from FPGA) 11 | | H4 | TX11_N | Transmit SERDES Lane (from FPGA) 11 |
 | I4 | TX11_P | Transmit SERDES Lane (from FPGA) 11 | | I4 | TX11_P | Transmit SERDES Lane (from FPGA) 11 |
 | J4 | GROUND | Digital Ground  | | J4 | GROUND | Digital Ground  |
-| K4 | RX7_N | Receive SERDES Lane (into FPGA) 7 | +| K4 | RX7_N | Receive SERDES Lane (into FPGA) 7* | 
-| L4 | RX7_P | Receive SERDES Lane (into FPGA) 7 |+| L4 | RX7_P | Receive SERDES Lane (into FPGA) 7* |
 | M4 | GROUND | Digital Ground  | | M4 | GROUND | Digital Ground  |
 | N4 | TX3_N | Transmit SERDES Lane (from FPGA) 3 | | N4 | TX3_N | Transmit SERDES Lane (from FPGA) 3 |
Line 134: Line 144:
 | B5 | +6V0 | +6V Power | | B5 | +6V0 | +6V Power |
 | C5 | GROUND | Digital Ground | | C5 | GROUND | Digital Ground |
-| D5 | RX16_N | Receive SERDES Lane (into FPGA) 16 | +| D5 | RX16_N | Receive SERDES Lane (into FPGA) 16* | 
-| E5 | RX16_P | Receive SERDES Lane (into FPGA) 16 |+| E5 | RX16_P | Receive SERDES Lane (into FPGA) 16* |
 | F5 | GROUND | Digital Ground | | F5 | GROUND | Digital Ground |
 | G5 | TX12_N | Transmit SERDES Lane (from FPGA) 12 | | G5 | TX12_N | Transmit SERDES Lane (from FPGA) 12 |
 | H5 | TX12_P | Transmit SERDES Lane (from FPGA) 12 | | H5 | TX12_P | Transmit SERDES Lane (from FPGA) 12 |
 | I5 | GROUND | Digital Ground | | I5 | GROUND | Digital Ground |
-| J5 | RX8_N | Receive SERDES Lane (into FPGA) 8 | +| J5 | RX8_N | Receive SERDES Lane (into FPGA) 8* | 
-| K5 | RX8_P | Receive SERDES Lane (into FPGA) 8 |+| K5 | RX8_P | Receive SERDES Lane (into FPGA) 8* |
 | L5 | GROUND | Digital Ground | | L5 | GROUND | Digital Ground |
 | M5 | TX4_N | Transmit SERDES Lane (from FPGA) 4 | | M5 | TX4_N | Transmit SERDES Lane (from FPGA) 4 |
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 | F6 | TX13_P | Transmit SERDES Lane (from FPGA) 13 | | F6 | TX13_P | Transmit SERDES Lane (from FPGA) 13 |
 | G6 | GROUND | Digital Ground | | G6 | GROUND | Digital Ground |
-| H6 | RX9_N | Receive SERDES Lane (into FPGA) 9 | +| H6 | RX9_N | Receive SERDES Lane (into FPGA) 9* | 
-| I6 | RX9_P | Receive SERDES Lane (into FPGA) 9 |+| I6 | RX9_P | Receive SERDES Lane (into FPGA) 9* |
 | J6 | GROUND | Digital Ground  | | J6 | GROUND | Digital Ground  |
 | K6 | TX5_N | Transmit SERDES Lane (from FPGA) 5 | | K6 | TX5_N | Transmit SERDES Lane (from FPGA) 5 |
 | L6 | TX5_P | Transmit SERDES Lane (from FPGA) 5 | | L6 | TX5_P | Transmit SERDES Lane (from FPGA) 5 |
 | M6 | GROUND | Digital Ground  | | M6 | GROUND | Digital Ground  |
-| N6 | RX1_N | Receive SERDES Lane (into FPGA) 1 | +| N6 | RX1_N | Receive SERDES Lane (into FPGA) 1* | 
-| O6 | RX1_P | Receive SERDES Lane (into FPGA) 1 | +| O6 | RX1_P | Receive SERDES Lane (into FPGA) 1* | 
-| A7 | CS3 | SPI Chip Select 3 | +| A7 | CS3 | SPI Chip Select 3† | 
-| B7 | CS6 | SPI Chip Select 6 |+| B7 | CS6 | SPI Chip Select 6† |
 | C7 | GROUND | Digital Ground | | C7 | GROUND | Digital Ground |
 | D7 | TX14_N | Transmit SERDES Lane (from FPGA) 14 | | D7 | TX14_N | Transmit SERDES Lane (from FPGA) 14 |
 | E7 | TX14_P | Transmit SERDES Lane (from FPGA) 14 | | E7 | TX14_P | Transmit SERDES Lane (from FPGA) 14 |
 | F7 | GROUND | Digital Ground | | F7 | GROUND | Digital Ground |
-| G7 | RX10_N | Receive SERDES Lane (into FPGA) 10 | +| G7 | RX10_N | Receive SERDES Lane (into FPGA) 10* | 
-| H7 | RX10_P | Receive SERDES Lane (into FPGA) 10 |+| H7 | RX10_P | Receive SERDES Lane (into FPGA) 10* |
 | I7 | GROUND | Digital Ground | | I7 | GROUND | Digital Ground |
 | J7 | TX6_N | Transmit SERDES Lane (from FPGA) 6 | | J7 | TX6_N | Transmit SERDES Lane (from FPGA) 6 |
 | K7 | TX6_P | Transmit SERDES Lane (from FPGA) 6 | | K7 | TX6_P | Transmit SERDES Lane (from FPGA) 6 |
 | L7 | GROUND | Digital Ground | | L7 | GROUND | Digital Ground |
-| M7 | RX2_N | Receive SERDES Lane (into FPGA) 2 | +| M7 | RX2_N | Receive SERDES Lane (into FPGA) 2* | 
-| N7 | RX2_P | Receive SERDES Lane (into FPGA) 2 |+| N7 | RX2_P | Receive SERDES Lane (into FPGA) 2* |
 | O7 | GROUND | Digital Ground | | O7 | GROUND | Digital Ground |
-| A8 | CS2 | SPI Chip Select 2 | +| A8 | CS2 | SPI Chip Select 2† | 
-| B8 | CS5 | SPI Chip Select 5 | +| B8 | CS5 | SPI Chip Select 5† | 
-| C8 | CS7 | SPI Chip Select 7 |+| C8 | CS7 | SPI Chip Select 7† |
 | D8 | GROUND | Digital Ground | | D8 | GROUND | Digital Ground |
 | E8 | TX15_N | Transmit SERDES Lane (from FPGA) 15 | | E8 | TX15_N | Transmit SERDES Lane (from FPGA) 15 |
 | F8 | TX15_P | Transmit SERDES Lane (from FPGA) 15 | | F8 | TX15_P | Transmit SERDES Lane (from FPGA) 15 |
 | G8 | GROUND  | Digital Ground | | G8 | GROUND  | Digital Ground |
-| H8 | RX11_N | Receive SERDES Lane (into FPGA) 11 | +| H8 | RX11_N | Receive SERDES Lane (into FPGA) 11* | 
-| I8 | RX11_P | Receive SERDES Lane (into FPGA) 11 |+| I8 | RX11_P | Receive SERDES Lane (into FPGA) 11* |
 | J8 | GROUND | Digital Ground  | | J8 | GROUND | Digital Ground  |
 | K8 | TX7_N | Transmit SERDES Lane (from FPGA) 7 | | K8 | TX7_N | Transmit SERDES Lane (from FPGA) 7 |
 | L8 | TX7_P | Transmit SERDES Lane (from FPGA) 7 | | L8 | TX7_P | Transmit SERDES Lane (from FPGA) 7 |
 | M8 | GROUND | Digital Ground  | | M8 | GROUND | Digital Ground  |
-| N8 | RX3_N | Receive SERDES Lane (into FPGA) 3 | +| N8 | RX3_N | Receive SERDES Lane (into FPGA) 3* | 
-| O8 | RX3_P | Receive SERDES Lane (into FPGA) 3 | +| O8 | RX3_P | Receive SERDES Lane (into FPGA) 3* | 
-| A9 | CS1 | SPI Chip Select 1 | +| A9 | CS1 | SPI Chip Select 1† | 
-| B9 | CS4 | SPI Chip Select 4 |+| B9 | CS4 | SPI Chip Select 4† |
 | C9 | GROUND | Digital Ground | | C9 | GROUND | Digital Ground |
 | D9 | TX16_N | Transmit SERDES Lane (from FPGA) 16 | | D9 | TX16_N | Transmit SERDES Lane (from FPGA) 16 |
 | E9 | TX16_P | Transmit SERDES Lane (from FPGA) 16 | | E9 | TX16_P | Transmit SERDES Lane (from FPGA) 16 |
 | F9 | GROUND | Digital Ground | | F9 | GROUND | Digital Ground |
-| G9 | RX12_N | Receive SERDES Lane (into FPGA) 12 | +| G9 | RX12_N | Receive SERDES Lane (into FPGA) 12* | 
-| H9 | RX12_P | Receive SERDES Lane (into FPGA) 12 |+| H9 | RX12_P | Receive SERDES Lane (into FPGA) 12* |
 | I9 | GROUND | Digital Ground | | I9 | GROUND | Digital Ground |
 | J9 | TX8_N | Transmit SERDES Lane (from FPGA) 8 | | J9 | TX8_N | Transmit SERDES Lane (from FPGA) 8 |
 | K9 | TX8_P | Transmit SERDES Lane (from FPGA) 8 | | K9 | TX8_P | Transmit SERDES Lane (from FPGA) 8 |
 | L9 | GROUND | Digital Ground | | L9 | GROUND | Digital Ground |
-| M9 | RX4_N | Receive SERDES Lane (into FPGA) 4 | +| M9 | RX4_N | Receive SERDES Lane (into FPGA) 4* | 
-| N9 | RX4_P | Receive SERDES Lane (into FPGA) 4 |+| N9 | RX4_P | Receive SERDES Lane (into FPGA) 4* |
 | O9 | GROUND | Digital Ground | | O9 | GROUND | Digital Ground |
-| A10 | MISO | SPI Master-In, Slave-Out Data| +| A10 | MISO | SPI Master-In, Slave-Out Data†| 
-| B10 | MOSI | SPI Master-Out, Slave-In Data| +| B10 | MOSI | SPI Master-Out, Slave-In Data†| 
-| C10 | SCLK | SPI Clock |+| C10 | SCLK | SPI Clock† |
 | D10 | GROUND | Digital Ground | | D10 | GROUND | Digital Ground |
-| E10 | ALIGN_RX_N | SYSREF clock input for Rx | +| E10 | ALIGN_RX_N | SYSREF clock input for Rx* | 
-| F10 | ALIGN_RX_P | SYSREF clock input for Rx |+| F10 | ALIGN_RX_P | SYSREF clock input for Rx* |
 | G10 | GROUND  | Digital Ground | | G10 | GROUND  | Digital Ground |
-| H10 | FRAME_RX_N | Device clock input for Rx | +| H10 | FRAME_RX_N | Device clock input for Rx* | 
-| I10 | FRAME_RX_P | Device clock input for Rx |+| I10 | FRAME_RX_P | Device clock input for Rx* |
 | J10 | GROUND | Digital Ground  | | J10 | GROUND | Digital Ground  |
-| K10 | RXSYNC2_N | SYNC input for Rx (secondary) | +| K10 | RXSYNC2_N | SYNC input for Rx (secondary)* | 
-| L10 | RXSYNC2_P | SYNC input for Rx (secondary) |+| L10 | RXSYNC2_P | SYNC input for Rx (secondary)* |
 | M10 | GROUND | Digital Ground  | | M10 | GROUND | Digital Ground  |
-| N10 | RXSYNC1_N | SYNC input for Rx | +| N10 | RXSYNC1_N | SYNC input for Rx* | 
-| O10 | RXSYNC1_P | SYNC input for Rx |+| O10 | RXSYNC1_P | SYNC input for Rx* |
  
 +//* The RX SERDES lines are not enabled, and can not be used with JESD204 ADCs//
 +
 +//† The SPI lines are not enabled. Communication with parts on the evaluation board is performed over the I2C link, and converted into SPI on the evaluation board//
 ====== Firmware Update ====== ====== Firmware Update ======
 The firmware of the DPG3 can be updated when new features or fixes are available. To update the firmware, click the //Advanced/Debug// button in DPGDownloader. Click the //Update// button in the Firmware section, and select the new firmware file. Do not interrupt the firmware update process. The unit may become inoperable if the update process is interrupted. The firmware of the DPG3 can be updated when new features or fixes are available. To update the firmware, click the //Advanced/Debug// button in DPGDownloader. Click the //Update// button in the Firmware section, and select the new firmware file. Do not interrupt the firmware update process. The unit may become inoperable if the update process is interrupted.
 +
 +====== Legacy CMOS Evaluation Boards======
 +Some legacy evaluation boards for DACs with a CMOS data interface use a ribbon cable to connect to a pattern generator, instead of connecting directly. To use these boards on a DPG3, an adapter board is required. Please contact [[mailto:dpg.support@analog.com|DPG Support]] to request this adapter board.
  
 ====== Support ====== ====== Support ======
 Please contact [[mailto:dpg.support@analog.com|DPG Support]] with any additional questions regarding the DPG or DAC Software Suite. Please contact [[mailto:dpg.support@analog.com|DPG Support]] with any additional questions regarding the DPG or DAC Software Suite.
  

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