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resources:eval:ad9914-user-guide [29 Nov 2016 14:45] – [Evaluation Board Software] Jeff Keipresources:eval:ad9914-user-guide [09 Jan 2021 00:22] (current) – user interwiki links Robin Getz
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-====== AD9914 Evaluation Board User Guide ======+====== AD9914/AD9915 Evaluation Board User Guide ======
  
 ===== Features===== ===== Features=====
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 After the installation of the evaluation software is complete, follow these steps to install the device driver:  After the installation of the evaluation software is complete, follow these steps to install the device driver: 
  
-  -Power up the evaluation board and apply the REF CLK source. See the [[http://wiki.analog.com/resources/eval/ad9914-user-guide#evaluation_board_hardware|Evaluation Board Hardware]] section for properly powering the evaluation board.+  -Power up the evaluation board and apply the REF CLK source. See the [[/resources/eval/ad9914-user-guide#evaluation_board_hardware|Evaluation Board Hardware]] section for properly powering the evaluation board.
   - Connect the evaluation board to the computer via the USB port using the USB cable included in the evaluation board kit. When the USB connection is recognized, a green LED light (D200) illuminates and the **Found New Hardware Wizard** dialog box appears.   - Connect the evaluation board to the computer via the USB port using the USB cable included in the evaluation board kit. When the USB connection is recognized, a green LED light (D200) illuminates and the **Found New Hardware Wizard** dialog box appears.
   - Click **Next** to continue installing the new driver.    - Click **Next** to continue installing the new driver. 
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 ===== Evaluation Board Hardware ===== ===== Evaluation Board Hardware =====
  
-The evaluation board provides all of the support circuitry required to operate the [[adi>AD9914|AD9914]] in its various modes and configurations. Figure 1 shows the typical bench characterization connections used to evaluate the ac performance. +The evaluation board provides all of the support circuitry required to operate the [[adi>AD9914|AD9914]] and [[adi>AD9915|AD9915]] in their various modes and configurations. Figure 1 shows the typical bench characterization connections used to evaluate the ac performance. 
  
 ==== Power Supplies ==== ==== Power Supplies ====
  
-The [[adi>AD9914|AD9914]] evaluation board has one power supply connector labeled P300 to power the USB interface circuitry and the [[adi>AD9914|AD9914]].  This connector has four pins; connect individual wires back to power supplies to power the [[adi>AD9914|AD9914]] evaluation board. Table 1 shows the necessary connections and the appropriate supply voltage+The [[adi>AD9914|AD9914]] evaluation board has one power supply connector labeled P300 to power the USB interface circuitry and the [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]].  This connector has four pins; connect individual wires back to power supplies to power the evaluation board. Table 1 shows the necessary connections and the appropriate supply voltage
 \\ \\
  
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 ==== Input Reference Clock Signal ==== ==== Input Reference Clock Signal ====
-The [[adi>AD9914|AD9914]] architecture provides the user with two options when providing an input clock signal to the part:  +The [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]] architecture provides the user with two options when providing an input clock signal to the part:  
-  * Connect a high frequency input clock signal up to 3.5 GHz to J104. +  * Connect a high frequency input clock signal up to 3.5/2.5 GHz to J104. 
   * Connect a lower input reference frequency to J104 and enable the internal clock multiplier (PLL).    * Connect a lower input reference frequency to J104 and enable the internal clock multiplier (PLL). 
 The maximum frequency rate of the PFD of the internal PLL is 125 MHz. The maximum frequency rate of the PFD of the internal PLL is 125 MHz.
 The input clock to the DDS is called the REF CLK. The internal system clock runs at the REF CLK rate if the internal REF CLK multiplier (PLL) is disabled.  Otherwise, the internal system clock runs at the output frequency rate of the PLL. The input clock to the DDS is called the REF CLK. The internal system clock runs at the REF CLK rate if the internal REF CLK multiplier (PLL) is disabled.  Otherwise, the internal system clock runs at the output frequency rate of the PLL.
-Note that the input clock path on the [[adi>AD9914|AD9914]] evaluation board uses an [[adi>ADCLK925|ADCLK925]] clock buffer to drive the [[adi>AD9914|AD9914]] differentially. Therefore, if the input signal into the [[adi>ADCLK925|ADCLK925]] has a slow slew rate, the in-close phase noise performance of the [[adi>AD9914|AD9914]] may be dramatically limited by the [[adi>ADCLK925|ADCLK925]]. +Note that the input clock path on the evaluation board uses an [[adi>ADCLK925|ADCLK925]] clock buffer to drive the [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]] differentially. Therefore, if the input signal into the [[adi>ADCLK925|ADCLK925]] has a slow slew rate, the in-close phase noise performance of the [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]] may be dramatically limited by the [[adi>ADCLK925|ADCLK925]]. 
  
 Refer to the [[adi>ADCLK925|ADCLK925]] data sheet for details on the maximum input speeds and input sensitivities.  Refer to the [[adi>ADCLK925|ADCLK925]] data sheet for details on the maximum input speeds and input sensitivities. 
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 The main output signal of the DDS is the DAC output. Note that the output of the DDS may or may not have a DAC reconstruction filter after the balun on the evaluation board depending on the revision of the board. The main output signal of the DDS is the DAC output. Note that the output of the DDS may or may not have a DAC reconstruction filter after the balun on the evaluation board depending on the revision of the board.
 ==== Jumper Settings ==== ==== Jumper Settings ====
-The jumpers on the [[adi>AD9914|AD9914]] evaluation board are factory set so that the board is ready to use with PC control. The [[adi>AD9914|AD9914]] software GUI operates the evaluation board in a serial interface only; however, you can also opt to use an alternative external control. Note that this user guide does not cover all aspects of externally controlling the [[adi>AD9914|AD9914]] evaluation board. +The jumpers on the evaluation board are factory set so that the board is ready to use with PC control. The software GUI operates the evaluation board in a serial interface only; however, you can also opt to use an alternative external control. Note that this user guide does not cover all aspects of externally controlling the evaluation board. 
  
-If you tri-state the USB circuitry to drive the board externally, you must control all tri-stated inputs to the [[adi>AD9914|AD9914]]. Otherwise, the device may not response to the external stimulus. For example, if the master reset input or the EXT_PWR_DWN input are floating, any external programming will have intermittent issues. All [[adi>AD9914|AD9914]] digital inputs are accessible via the provided header connectors.+If you tri-state the USB circuitry to drive the board externally, you must control all tri-stated inputs to the [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]]. Otherwise, the device may not response to the external stimulus. For example, if the master reset input or the EXT_PWR_DWN input are floating, any external programming will have intermittent issues. All digital inputs are accessible via the provided header connectors.
 \\ \\
  
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 For external control                For external control               
   - Set jumpers P203, P204, P205 to Disable.    - Set jumpers P203, P204, P205 to Disable. 
-  - Control the [[adi>AD9914|AD9914]] via external header connectors.                    +  - Control the [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]] via external header connectors.                    
 ==== External Header Connectors ==== ==== External Header Connectors ====
-The external I/O control headers provide a parallel or serial communication interface for the [[adi>AD9914|AD9914]] when the part is under the command of an external controller.  In addition, the headers provide an interface for modulation data depending on the setting of the function pins. See the [[adi>AD9914|AD9914]] data sheet for more details on the function pins settings.+The external I/O control headers provide a parallel or serial communication interface for the [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]] when the part is under the command of an external controller.  In addition, the headers provide an interface for modulation data depending on the setting of the function pins. See the data sheet for more details on the function pins settings.
 === Disabling Software GUI Control === === Disabling Software GUI Control ===
 Disabling the ICs on the evaluation board allows operation of the board with an external serial or parallel control by configuring each buffer in its high impedance state by its nearby jumper. Disabling the ICs on the evaluation board allows operation of the board with an external serial or parallel control by configuring each buffer in its high impedance state by its nearby jumper.
 ==== USB Port ==== ==== USB Port ====
-When the part is under PC control (default mode), the evaluation board communicates with the [[adi>AD9914|AD9914]] via the USB port.+When the part is under PC control (default mode), the evaluation board communicates with the [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]] via the USB port.j
  
 ===== Modes of Operation ===== ===== Modes of Operation =====
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 ====Profile Mode====  ====Profile Mode==== 
  
-In profile mode, the three DDS signal control parameters (frequency, phase offset, and amplitude scaling) are supplied directly from 1 of 8 internal profile registers. A profile is an independent register that contains all three control parameters. You can use a profile register to output a single tone frequency or use multiple preprogram profile registers and the profile pins to hop between frequencies, phase offsets and/or different amplitude settings. The following example are the steps to program a single profile to output a single tone frequency using the [[adi>AD9914|AD9914]] software GUI.+In profile mode, the three DDS signal control parameters (frequency, phase offset, and amplitude scaling) are supplied directly from 1 of 8 internal profile registers. A profile is an independent register that contains all three control parameters. You can use a profile register to output a single tone frequency or use multiple preprogram profile registers and the profile pins to hop between frequencies, phase offsets and/or different amplitude settings. The following example are the steps to program a single profile to output a single tone frequency using the software GUI.
  
  ===Single Tone Operation===  ===Single Tone Operation===
-   -Power up the [[adi>AD9914|AD9914]] evaluation board and apply the REF CLK source to clock the [[adi>AD9914|AD9914]].     +   -Power up the evaluation board and apply the REF CLK source to clock the [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]].     
-   -Launch the [[adi>AD9914|AD9914]] evaluation software. After the software recongnizes the evaluation board, click the master reset icon in the main tool bar of the software GUI (labeled 1 in Figure 7). The master reset clears all memory elements and sets the registers to default values.+   -Launch the evaluation software. After the software recongnizes the evaluation board, click the master reset icon in the main tool bar of the software GUI (labeled 1 in Figure 7). The master reset clears all memory elements and sets the registers to default values.
    -Enter the desired REF CLK frequency value in the **External Clock** box. If the internal PLL is to be used, enable and load those desired PLL settings at this time.    -Enter the desired REF CLK frequency value in the **External Clock** box. If the internal PLL is to be used, enable and load those desired PLL settings at this time.
    -After the desired system clock frequency appears in the main tool bar of the software GUI, click the DAC calibration icon (labeled 3 in Figure 7). The DAC CAL is required once for the initial setup and/or every time the REF CLK frequency is changed.    -After the desired system clock frequency appears in the main tool bar of the software GUI, click the DAC calibration icon (labeled 3 in Figure 7). The DAC CAL is required once for the initial setup and/or every time the REF CLK frequency is changed.
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    -View the DAC output single tone frequency performance via an oscilloscope or spectrum analyzer.    -View the DAC output single tone frequency performance via an oscilloscope or spectrum analyzer.
  
-To select a profile other than Profile 0, use the **Selected Profile** drop-down menu. Note that, unfortunately, the profile pin signals are sent asynchronously from the buffer ICs on the evaluation board to the [[adi>AD9914|AD9914]] profile pins. Thus, it is possible that the profile found may not be the profile you selected because the profile signals are not synchronous to the SYNC_CLK. If the selected profile setting does not point to the correct profile settings chosen, send an IO_UPDATE or click **Load** tocorrect the issue. This would not be an issue if the profile signals were sychrnonously transmitted to the [[adi>AD9914|AD9914]]. +To select a profile other than Profile 0, use the **Selected Profile** drop-down menu. Note that, unfortunately, the profile pin signals are sent asynchronously from the buffer ICs on the evaluation board to the profile pins. Thus, it is possible that the profile found may not be the profile you selected because the profile signals are not synchronous to the SYNC_CLK. If the selected profile setting does not point to the correct profile settings chosen, send an IO_UPDATE or click **Load** tocorrect the issue. This would not be an issue if the profile signals were sychrnonously transmitted to the [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]]. 
 ===Profile Data Entry=== ===Profile Data Entry===
 \\ <WRAP centeralign> \\ <WRAP centeralign>
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 </WRAP> </WRAP>
  
-The **Frequency** box is used to set the frequency generated by the DDS. The input values are in megahertz. Refer to the [[adi>AD9914|AD9914]] data sheet for the acceptable range of output frequencies.+The **Frequency** box is used to set the frequency generated by the DDS. The input values are in megahertz. Refer to the data sheet for the acceptable range of output frequencies.
  
 The **Phase Offset** box controls the phase of the DDS output. The input is in degrees and can be changed from 0° to 360° with 16-bit resolution. The **Phase Offset** box controls the phase of the DDS output. The input is in degrees and can be changed from 0° to 360° with 16-bit resolution.
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 ===Control Tab=== ===Control Tab===
  
-The **Control** tab provides control of the internal PLL, parallel port, auxiliary functions, I/O control, power-down functions, output shift keying (OSK), clock calibration, and multichip sync function of the [[adi>AD9914|AD9914]].+The **Control** tab provides control of the internal PLL, parallel port, auxiliary functions, I/O control, power-down functions, output shift keying (OSK), clock calibration, and multichip sync function of the [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]].
  
 ===Profiles Tab=== ===Profiles Tab===
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 ===Sweep Tab=== ===Sweep Tab===
  
-Digital ramp generator (DRG) is synonymous with linear sweep. The ramp generation parameters in the **Sweep** tab allow you to control both the rising and falling slopes of the ramp, the upper and lower boundaries of the ramp, the step size and step rate of the rising portion of the ramp, and the step size and step rate of the falling portion of the ramp. This is digitally generated with a 32-bit output resolution that can be programmed to represent frequency, phase, or amplitude. Refer to the [[adi>AD9914|AD9914]] data sheet for more information on DRG.+Digital ramp generator (DRG) is synonymous with linear sweep. The ramp generation parameters in the **Sweep** tab allow you to control both the rising and falling slopes of the ramp, the upper and lower boundaries of the ramp, the step size and step rate of the rising portion of the ramp, and the step size and step rate of the falling portion of the ramp. This is digitally generated with a 32-bit output resolution that can be programmed to represent frequency, phase, or amplitude. Refer to the data sheet for more information on DRG.
 ===Modulus Tab=== ===Modulus Tab===
  
-The Modulus tab allows you to enable programmable modulus mode and to alter the frequency equation of the DDS core, making it possible to implement fractions that are not restricted to a power of 2 in the denominator. See the [[adi>AD9914|AD9914]]data sheet for more details.+The Modulus tab allows you to enable programmable modulus mode and to alter the frequency equation of the DDS core, making it possible to implement fractions that are not restricted to a power of 2 in the denominator. See the data sheet for more details.
  
 ===Debug Tab=== ===Debug Tab===
  
-The Debug tab provides complete direct access to the register map as well as control of many external pins. The Debug tab is intended for debugging issues with the [[adi>AD9914|AD9914]]. Although this tab can be used for all programming, it is not user friendly for programming purposes and, therefore, using the **Debug** tab for purposes other than debugging may result in improper programming of reserved bits. +The Debug tab provides complete direct access to the register map as well as control of many external pins. The Debug tab is intended for debugging issues with the [[adi>AD9914|AD9914]]/[[adi>AD9915|AD9915]]. Although this tab can be used for all programming, it is not user friendly for programming purposes and, therefore, using the **Debug** tab for purposes other than debugging may result in improper programming of reserved bits. 
  
  
resources/eval/ad9914-user-guide.1480427132.txt.gz · Last modified: 29 Nov 2016 14:45 by Jeff Keip

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