Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
resources:eval:ad9694-500ebz [19 Feb 2019 17:33] – [AD9694 Evaluation Board] Alan Yuresources:eval:ad9694-500ebz [20 May 2022 17:52] (current) – [Visual Analog Setup] Judy Chui
Line 8: Line 8:
 The [[adi>AD9694|AD9694]] data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at  [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. For additional information or questions, send an email to highspeed.converters@analog.com. The [[adi>AD9694|AD9694]] data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at  [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. For additional information or questions, send an email to highspeed.converters@analog.com.
 ===== AD9694 Evaluation Board ===== ===== AD9694 Evaluation Board =====
 +The images below show the location and position of the jumpers on the old (first image) and new (second image) versions of the [[adi>AD9694|AD9694-500EBZ]].
 {{ :resources:eval:ad9694_jumpers.jpg?direct800 |}}<WRAP centeralign> {{ :resources:eval:ad9694_jumpers.jpg?direct800 |}}<WRAP centeralign>
 //[[adi>AD9694|AD9694]] Evaluation Board (old version)//</WRAP> //[[adi>AD9694|AD9694]] Evaluation Board (old version)//</WRAP>
-{{:resources:eval:ad9694_jumpers_new_board.jpg?direct800|}}<WRAP centeralign>+{{ :resources:eval:ad9694_jumpers_new_board.jpg?direct800 |}}<WRAP centeralign>
 //[[adi>AD9694|AD9694]] Evaluation Board (new version)//</WRAP> //[[adi>AD9694|AD9694]] Evaluation Board (new version)//</WRAP>
 ===== Typical Measurement Setup ===== ===== Typical Measurement Setup =====
-The [[adi>AD9694|AD9694-500EBZ]] can be evaluated using the [[ads7-v2|ADS7-V2EBZ]] FPGA data capture board. The figure below shows the [[adi>AD9694|AD9694-500EBZ]] connected to the [[ads7-v2|ADS7-V2EBZ]]. +The [[adi>AD9694|AD9694-500EBZ]] can be evaluated using the [[ads7-v2|ADS7-V2EBZ]] FPGA data capture board. The figures below show the [[adi>AD9694|AD9694-500EBZ]] connected to the [[ads7-v2|ADS7-V2EBZ]]. If using the old version of the board, refer to the first image for connections, otherwise if using the new version of the board, refer to the second image.
 {{ :resources:eval:ad9694_connection.png?direct&800 |}}<WRAP centeralign> {{ :resources:eval:ad9694_connection.png?direct&800 |}}<WRAP centeralign>
-//Evaluation Board Connection—[[adi>AD9694|AD9694-500EBZ]]//+//(Old) Evaluation Board Connection—[[adi>AD9694|AD9694-500EBZ]]// 
 +</WRAP> 
 +{{ :resources:eval:ad9694_connection_new_board.jpg?direct&800 |}}<WRAP centeralign> 
 +//(New) Evaluation Board Connection—[[adi>AD9694|AD9694-500EBZ]]//
 </WRAP> </WRAP>
 ===== Features ===== ===== Features =====
Line 34: Line 38:
 ===== Software Needed ===== ===== Software Needed =====
   * VisualAnalog [[ftp://ftp.analog.com/pub/HSSP_SW/VisualAnalog/VisualAnalog_Setup.exe]]      * VisualAnalog [[ftp://ftp.analog.com/pub/HSSP_SW/VisualAnalog/VisualAnalog_Setup.exe]]   
-  * ACE [[https://wiki.analog.com/resources/tools-software/ace]]+  * ACE [[/resources/tools-software/ace]]
 ===== Design and Integration Files ===== ===== Design and Integration Files =====
-  *[[https://wiki.analog.com/_media/eval/9694_board_files_ce04.zip|AD9694CE04A schematic, BOM, layout files]]+  * {{ :eval:9694_board_files_ce04.zip |AD9694CE04A schematic, BOM, layout files}}
 ===== Equipment Needed ===== ===== Equipment Needed =====
   * Analog signal source and antialiasing filter   * Analog signal source and antialiasing filter
Line 59: Line 63:
   - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J203 and set the amplitude to 14dBm. This is the ADC Sample Clock.   - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J203 and set the amplitude to 14dBm. This is the ADC Sample Clock.
   - On the [[ads7-v2|ADS7-V2EBZ]] data capture board, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16 </m>//(Default Nprime = 16)//</WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP>   - On the [[ads7-v2|ADS7-V2EBZ]] data capture board, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16 </m>//(Default Nprime = 16)//</WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP>
-  - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J100. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) If providing an input clock with a divide-by-1 setting in the AD9694 make sure the clock source has a 50% duty cycle.  For optimum SNR performance use the clock divider with a divide ratio of 2 or higher to minimize the impact of the phase noise from the input clock source.+  - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J101. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) If providing an input clock with a divide-by-1 setting in the AD9694 make sure the clock source has a 50% duty cycle.  For optimum SNR performance use the clock divider with a divide ratio of 2 or higher to minimize the impact of the phase noise from the input clock source.
   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to J102. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to J102. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)
   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel C to J104. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel C to J104. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)
-  - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel D to J106. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)+  - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel D to J107. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)
 ==== Visual Analog Setup ==== ==== Visual Analog Setup ====
   - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> VisualAnalog <m>right</m> VisualAnalog   - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> VisualAnalog <m>right</m> VisualAnalog
   - On the VisualAnalog “New Canvas” window, and select the desired canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD9694 in the same chip operating mode with the same decimation rate. If Pair AB is in full bandwidth mode then Pair CD must also be in full bandwidth mode.  If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ :resources:eval:newcanvas9694.jpg?nolink |}}<WRAP centeralign>//Selecting the [[adi>AD9694|AD9694]] canvas //</WRAP>   - On the VisualAnalog “New Canvas” window, and select the desired canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD9694 in the same chip operating mode with the same decimation rate. If Pair AB is in full bandwidth mode then Pair CD must also be in full bandwidth mode.  If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ :resources:eval:newcanvas9694.jpg?nolink |}}<WRAP centeralign>//Selecting the [[adi>AD9694|AD9694]] canvas //</WRAP>
   - Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed. {{ :resources:eval:9694_program_FPGA.png?nolink |}}<WRAP centeralign>//Programming the [[ads7-v2|ADS7-V2EBZ]]//</WRAP>   - Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed. {{ :resources:eval:9694_program_FPGA.png?nolink |}}<WRAP centeralign>//Programming the [[ads7-v2|ADS7-V2EBZ]]//</WRAP>
-  - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to 2x the input clock. For example, if the input clock to the AD9694 is 368.64 MHz then set the **Clock Frequency (MHz)** to 737.28 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel).{{ :resources:eval:9694_data_capture_settings_general.png |}}<WRAP centeralign>//Changing the ADC Capture Settings//</WRAP>+  - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to match the sample clock. For example, if the sample clock of the AD9694 is 368.64 MHz then set the **Clock Frequency (MHz)** to 368.64 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel).{{ :resources:eval:9694_data_capture_settings_general.png |}}<WRAP centeralign>//Changing the ADC Capture Settings//</WRAP>
   - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Expanding Display in VA//</WRAP>   - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Expanding Display in VA//</WRAP>
-  - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked.+  - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is checked.
   - Click **OK**   - Click **OK**
 ==== ACE Setup ==== ==== ACE Setup ====
Line 102: Line 106:
     - When making changes to the DDC settings the **DDC Soft Reset** must be written afterwards.  To do so, select **DDC Held in Reset** from the drop down menu in the block diagram.  Then click **Apply Changes** in the upper left of the AD9694 Device view in ACE.  Next, select **Normal Operation** from the drop down menu in the block diagram and then click **Apply Changes** once again.  This process resets the DDC and then places the DDC back into normal operating mode.  This must be done for each pair (Pair AB and/or Pair CD) for which DDC changes have been applied. {{ :resources:eval:9694_ace_device_view_1ddc_complexinout_ddc_softreset.png?nolink |}}<WRAP centeralign>//Pair AB: Channel A and Channel B DDC0 Settings with DDC Soft Reset//</WRAP>     - When making changes to the DDC settings the **DDC Soft Reset** must be written afterwards.  To do so, select **DDC Held in Reset** from the drop down menu in the block diagram.  Then click **Apply Changes** in the upper left of the AD9694 Device view in ACE.  Next, select **Normal Operation** from the drop down menu in the block diagram and then click **Apply Changes** once again.  This process resets the DDC and then places the DDC back into normal operating mode.  This must be done for each pair (Pair AB and/or Pair CD) for which DDC changes have been applied. {{ :resources:eval:9694_ace_device_view_1ddc_complexinout_ddc_softreset.png?nolink |}}<WRAP centeralign>//Pair AB: Channel A and Channel B DDC0 Settings with DDC Soft Reset//</WRAP>
 ==== Obtaining an FFT - 1 DDC Per ADC Pair in Complex Mode with Decimation by 2 Mode ==== ==== Obtaining an FFT - 1 DDC Per ADC Pair in Complex Mode with Decimation by 2 Mode ====
-  - The first item to configure in Visual Analog is the input clock frequency.  This needs to be set to twice the frequency of the input clock.  Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog.  Also, make sure that the output data is set to *Ch. DDC0 Data*.{{ :resources:eval:6684_data_capture_settings_ddc0.png?nolink |}}<WRAP centeralign>//AD9694 FFT Data Capture Settings//</WRAP> +  - The first item to configure in Visual Analog is the input clock frequency.  This needs to be set to twice the frequency of the input clock.  Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the sample clock frequency so 368.64 is entered into VisualAnalog.  Also, make sure that the output data is set to *Ch. DDC0 Data*.{{ :resources:eval:6684_data_capture_settings_ddc0.png?nolink |}}<WRAP centeralign>//AD9694 FFT Data Capture Settings//</WRAP> 
-  - In this example, with an input clock of 368.64MHz, the output sample rate is 184.32MSPS.  The  JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.4.4 (L.M.F).  The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "Configuring the Board"). +  - In this example, with a sample clock of 368.64MHz, the output sample rate is 184.32MSPS.  The  JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.4.4 (L.M.F).  The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "Configuring the Board"). 
   - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:9694_2ddc_complex_inout_ncopassthrough_fft_fin345p1mhz.png?800 |}}<WRAP centeralign>//AD9694 FFT with DDC0 Enabled//</WRAP>   - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:9694_2ddc_complex_inout_ncopassthrough_fft_fin345p1mhz.png?800 |}}<WRAP centeralign>//AD9694 FFT with DDC0 Enabled//</WRAP>
   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Adjust the input signal to -1.4 dBFS or less in the FFT in Visual Analog (this accounts for the approximately -0.4 dB loss in the DDC. Recall that the mixing process incurs a 6dB additional loss; the signal amplitude is -7.4 dBFS in this plot.   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Adjust the input signal to -1.4 dBFS or less in the FFT in Visual Analog (this accounts for the approximately -0.4 dB loss in the DDC. Recall that the mixing process incurs a 6dB additional loss; the signal amplitude is -7.4 dBFS in this plot.
resources/eval/ad9694-500ebz.1550594026.txt.gz · Last modified: 19 Feb 2019 17:33 by Alan Yu

Page Tools