This user guide describes the AD9683 and AD6677 evaluation boards; AD9683-170EBZ, AD9683-250EBZ, and AD6677EBZ; which provide all of the support circuitry required to operate these parts in their various modes and configurations. The application software used to interface with the devices is also described.
The AD9683 and AD6677 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to email@example.com.
Before using the software for testing, configure the evaluation board as follows:
The evaluation board provides the support circuitry required to operate the AD9683 and AD6677 in their various modes and configurations. Figure 1 shows the typical bench characterization setup used to evaluate AC performance. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance.
See the evaluation board pages linked from the AD9683 and AD6677 product pages for the complete schematics and bill of materials (BOM). The evaluation board layout is available upon request. The layout diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters.
This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to a 100 V ac to 240 V ac, 47 Hz to 63 Hz wall outlet. The output from the supply is provided through a 2.1 mm inner diameter jack that connects to the printed circuit board (PCB) at P201. The 6 V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators that supply the proper bias to each of the various sections on the board.
The evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, remove the all the jumpers listed above (and in Table 1) to disconnect the outputs from the on-board LDOs. This enables the user to bias each section of the board individually. Use P1, P208, and P502 to connect a different supply for each section. A 1.8 V, 0.5 A supply is needed for 1.8 V_AVDD, 1.8 V_DVDD, and 1.8 V_DRVDD. Although the power supply requirements are the same for AVDD, DVDD, and DRVDD, it is recommended that separate supplies be used for both analog and digital domains. The DVDD and DRVDD voltages can be driven from the same power supply. The SPI and its level shifters and alternate clock options require a separate 3.3 V, 0.5 A analog supply. In addition, if using the AD9525 and/or the ADL5202, a separate 5.0 V, 0.5 A analog supply is required.
When connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA, or HP 8644B signal generators or an equivalent. Use a 1 m shielded, RG-58, 50 Ω coaxial cable for connecting to the evaluation board. Enter the desired frequency and amplitude (see the Specifications section in the data sheet of the respective part). When connecting the analog input source, use of a multipole, narrow-band band-pass filter with 50 Ω terminations is recommended. Analog Devices uses band-pass filters from TTE and K&L Microwave, Inc. Connect the filters directly to the evaluation board.
If an external clock source is used, it should also be supplied with a clean signal generator as previously specified. Analog Devices evaluation boards typically can accept ~2.8 V p-p or 13 dBm sine wave input for the clock.
The default setup uses the Analog Devices high speed converter evaluation platform (HSC-ADC-EVALDZ) for data capture. The serial JESD204B outputs from the ADC are routed to Connector P1002 using 100 Ω differential traces. For more information on the data capture board and its optional settings, visit www.analog.com/hsadcevalboard.
Set the jumper settings/link options on the evaluation board for the required operating modes before powering on the board. The functions of the jumpers are described in Table 1. Figure 2 shows the default jumper settings.
|P202||This jumper sets up the 5.0 V power supply voltage for the outputs of the on-board ADL5202. For the ADL5202 to work properly, its outputs must be tied to a 5.0 V power supply via the appropriate sized inductors. On the AD9683-170EBZ/AD9683-250EBZ/AD6677EBZ boards these inductors are 1 uH.|
|P209||This jumper sets up the 3.3V analog power supply voltage for the ADL5202.|
|P210||This jumper connects the DVDD power supply domain to the DRVDD power supply domain to power the JESD204B output drivers of the AD9683 and AD6677.|
|P205||This jumper connects the AVDD power supply domain of the AD9683 and AD6677.|
|P206||This jumper connects the DVDD power supply domain of the AD9683 and AD6677.|
|P204||This jumper sets up a 3.3 V digital power supply voltage for the AD9525 and also powers SPI related circuitry.|
|P504||This jumper connects the AD9683 and AD6677 external clock input to the reference clock input of the FPGA (for the JESD204B link) on the HSC-ADC-EVALDZ.|
Plug the switching power supply into a wall outlet rated at 100 V ac to 240 V ac, 47 Hz to 63 Hz. Connect the DC output connector to P101 on the evaluation board.
The analog input on the evaluation board is set up for a double balun-coupled analog input with a 50 Ω impedance. The default analog input configuration supports analog input frequencies of up to ~400 MHz. For additional information on recommended input networks, see the AD9683 and AD6677 data sheets.
Optionally, the AD9683 and AD6677 analog input can be configured to use the ADL5202 digitally controlled, variable gain wide bandwidth amplifier. The ADL5202 is included on the evaluation board at U401. The path into and out of the ADL5202 can be configured many different ways depending on the application; therefore, several of the components in the input and output path are left unpopulated. See the ADL5202 data sheet for additional information on this part and for configuring the inputs and outputs.
In order to connect the active path using the ADL5202 a few resistors need to be changed. First, remove C305 and C306. Then populate R311 and R312. These changes disconnect the passive input and connect the output of the ADL5202 to the analog inputs of the AD9683 and AD6677. Next, place the desired filter components at the output of the ADL5202. As mentioned, these are not populated by default since there are many different possibilities. J404 must also be populated so that the input of the ADL5202 can be driven with an external signal source.
The default clock input circuit connects to the Nyquist clock input of the AD9683 and AD6677. The clock is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T503) that adds a low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal before entering the ADC clock inputs. The AD9683 and AD6677 ADCs are equipped with an internal 8:1 clock divider to facilitate usage with higher frequency clocks. The clock input for the Nyquist clock is the CLK+ SMA connector.
The AD9683 and AD6677 are also equipped with a single-ended RF Clock input that can receive input frequencies from 625 MHz up to 1.5 GHz. This feature must be enabled via SPI and a clock of appropriate frequency must be connected to the RF_CLK SMA connector. The RF Clock circuitry within the AD9683 and AD6677 has a selectable /2 or /4 pre-divider in addition to the internal 8:1 clock divider to facilitate usage with higher frequency clocks up to 1.5 GHz.
To enable the power-down feature, add a shorting jumper across P3 (directly to the right of P209) at Pin 1 and Pin 2 to connect the PDWN pin to DRVDD.
To enable the reset feature, add a shorting jumper across P101 at Pin 1 and Pin 2 to connect the RSTB pin to GND.
After configuring the board, set up the ADC data capture using the following steps:
Figure 3. VisualAnalog, New Canvas Window
Figure 5. VisualAnalog ADC Data Capture Settings
Figure 6. VisualAnalog Window Toolbar, Collapsed Display
Figure 7. VisualAnalog, Main Window, Expanded Display
After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:
Figure 8. SPI Controller, CHIP ID(1) Box
Figure 10. SPI Controller, ADCBase0
Figure 11. SPI Controller, Example ADCBase1 Page
Figure 12. SPI Controller, Example ADCBase1 Page
The next step is to adjust the amplitude of the input signal for each channel as follows:
Figure 15. Typical FFT, AD9253
If the FFT plot appears abnormal, do the following:
If the FFT appears normal but the performance is poor, check the following:
If the FFT window remains blank after Run in VisualAnalog (see Figure 11) is clicked, do the following:
If VisualAnalog indicates that the FIFO Capture timed out, do the following: