This user guide describes the AD9257 and AD9637 evaluation boards, AD9257-65EBZ and AD9637-80EBZ, which provide the support circuitry required to operate these parts in their various modes and configurations. The application software used to interface with the devices is also described.
Though the information on this page applies generally to the currently released version of the AD9257-65EBZ and AD9637-80EBZ, the specifics (i.e. photos, jumper labels, etc.) are for the soon-to-be-released version. Information specifically for the released version can be found here quickstartguide_ad9257_ad9637_prb.pdf.
The AD9257 and AD9637 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to firstname.lastname@example.org.
Before using the software for testing, configure the evaluation board as follows:
The evaluation board provides the support circuitry required to operate the AD9257 and AD9637 in their various modes and configurations. Figure 1 shows the typical bench characterization setup used to evaluate AC performance. It is critical that the signal sources used for the analog input and clock have very low phase noise (ideally ~100 fs rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance.
See AD9257/9637 Design Support <Coming Soon> for the complete schematics and layout diagrams. These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters.
This evaluation board comes with a wall-mountable switching power supply that provides a 6V, 2A maximum output. Connect the supply to a 100V ac to 240V ac, 47Hz to 63Hz wall outlet. The output from the supply is provided through a 2.1mm inner diameter jack that connects to the printed circuit board (PCB) at P101. The 6V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators that supply the proper bias to each of the various sections on the board.
The evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, remove the E101, E102, E104, E105, E111, E112, E113, E114, E115 and E116 ferrite beads to disconnect the bench supply traces from the on-board LDOs. Note that in some board configurations some of these might already be uninstalled. P102 and P103 need to be installed to connect external bench supplies to the board. E106, E107, E108 and E109 need to be populated to connect P102 and P103 to the board power domains. A 1.8V , 0.5A supply is needed for 1.8V_DUT_AVDD and 1.8V_DRVDD. Although the voltage requirements are the same for 1.8V_DUT_AVDD and 1.8V_DRVDD, it is recommended that separate supplies be used for each of these.
Two additional supplies, 5.0V_AVDD and 3.3V_AVDD, are used to bias the optional input path amplifiers and optional AD9517-4 clock chip. If used, these supplies should each have at least 0.5A current capability.
When connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA, or an equivalent. Use a shielded, RG-58, 50Ω coaxial cable (optimally 1 m or shorter) for connecting to the evaluation board. Enter the desired frequency and amplitude (see the Specifications section in the data sheet of the respective part). When connecting the analog input source, use of a multipole, narrow-band band-pass filter with 50Ω terminations is recommended. Analog Devices uses band-pass filters from TTE and K&L Microwave, Inc. Connect the filters directly to the evaluation board.
If an external clock source is used, it should also be supplied with a clean signal generator as previously specified for the analog input signals. Analog Devices evaluation boards typically can accept ~2.8V p-p or 13 dBm sine wave input for the clock. If an external off-board clock source is used, remove the jumper on P601, and C1109, to disable and disconnect the on-board crystal oscillator.
The default setup uses the Analog Devices high speed converter evaluation platform (HSC-ADC-EVALCZ) for data capture. The serial LVDS outputs from the ADC are routed to Connector P1302 using 100Ω differential traces. For more information on the data capture board and its optional settings, visit www.analog.com/hsadcevalboard.
Set the jumper settings/link options on the evaluation board for the required operating modes before powering on the board. The functions of the jumpers are described in Table 1. Figure 2 shows the default jumper settings.
|J203||Use this jumper to power down the ADC. Using the SPI, the PDWN pin can be configured to be STBY (standby).|
|J1001 and J1002||These jumpers enable the optional ADL5565 amplifiers on Channels G and H, respectively. Connect pin 2 to pin 3 for default (amplifier disabled) operation.|
|J301||This jumper sets the ADC for SPI communications with the HSC-ADC-EVALCZ.
Connect Pin 1 to Pin 2 for SDIO, Pin 4 to Pin 5 for SCLK, and Pin 8 to Pin 9 for CSB.
|J1103||This jumper enables the on-board crystal oscillator. Remove this jumper if an external off-board clock source is used.|
|J202||This jumper selects between internal VREF and external VREF.
To choose the internal 1V reference, connect Pin 3 (DUT_SENSE) to Pin 5 (GND).
To use the on-board ADR130 1V reference, connect Pin 2 (DUT_SENSE) to Pin 1 (AVDD), and connect Pin 4 (DUT_VREF) to Pin 6 (EXT_REF).
To apply a reference voltage from an external off-board source, connect Pin 2 (DUT_SENSE) to Pin 1 (AVDD) and apply the reference voltage to Pin 4 (DUT_VREF). The AD9257 and AD9637 reference voltage is specified to be 1.0 V.
|P1201||Header to observe AD9517 (optional clock generator) Digital Lock Detect pins.|
Connect the switching power supply that is supplied in the evaluation kit between a rated 100V ac to 240V ac, 47Hz to 63Hz wall outlet and P101.
The eight channel inputs on the evaluation board are set up for a double balun-coupled analog input with a 50Ω impedance. The default analog input configuration supports analog input frequencies of up to ~200 MHz.
RBIAS has a default setting of 10 kΩ (R205) to ground and is used to set the ADC core bias current. Note that using a resistor value other than a 10kΩ, 1% resistor for RBIAS may degrade the performance of the device.
The default clock input circuit is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T1101) that adds a low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sinusoidal inputs. The transformer converts the single-ended input to a differential signal that is clipped by CR1101 before entering the ADC clock inputs. The AD9257 and AD9637 ADCs are equipped with an internal 8:1 clock divider to facilitate usage with higher frequency clocks. When using the internal divider and a higher input clock frequency, remove CR1101 to preserve the slew rate of the clock signal.
The AD9257-65EBZ and AD9637-80EBZ boards are set up to be clocked through the transformer-coupled input network from the crystal oscillator, Y1101. If a different clock source is desired, remove C1109 (optional) and Jumper J1103 to disable the oscillator from running and connect the external clock source to the SMA connector, J1102 (labeled CLK+).
The AD9257/AD9637 ADCs can operate in pin mode if there is no need to program and change the default modes of operation via the SPI. For applications that do not require SPI mode operation, the CSB pin is tied to 1.8V_DUT_AVDD by removing any jumper on Pin 8 of J301. In this configuration the SDIO/DFS pin controls the digital output format, and the SCLK/DTP pin controls the digital output test pattern. Table 2 and Table 3 specify the settings for pin mode operation.
|SDIO/DFS (J301 Pin 2) Voltage||Device Mode|
|1.8V_DUT_AVDD (jumper J301 Pin 2 to Pin 3)||Twos Complement|
|GND (“float” J301 Pin 2)||Offset Binary|
|SCLK/DTP (J301 Pin 5) Voltage||Output Format|
|GND (“float” J301 Pin 5)||Normal Operation|
|1.8V_DUT_AVDD (jumper J301 Pin 5 to Pin 6)||10 0000 0000 0000|
Note that the above settings only apply when CSB is tied high (J301 Pin 8 “floating”) at power up.
To operate the device under test (DUT) using the SPI, follow the jumper settings for J301 as shown in Table 1.
After configuring the board, set up the ADC data capture using the following steps:
Figure 3. VisualAnalog, New Canvas Window
Figure 5. VisualAnalog Window Toolbar, Collapsed Display
Figure 6. VisualAnalog, Main Window Expanded Display
After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:
Figure 7. SPI Controller, CHIP ID(1) Box
Figure 8. SPI Controller, New DUT Button
Figure 9. SPI Controller, CLOCK DIVIDE(B) Box
Figure 10. SPI Controller, Chip Power Mode - Digital Reset Selection
Figure 11. SPI Controller, Example ADC A Page
Figure 12. Run/Continuous Run Buttons (Encircled in Red) in VisualAnalog Toolbar, Collapsed Display
The next step is to adjust the amplitude of the input signal for each channel as follows:
Figure 13. Graph Window of VisualAnalog
Lack of SPI communication will cause difficulty in configuring the ADC.
If the FFT plot appears abnormal, do the following:
If the FFT appears normal but the performance is poor, check the following:
If the FFT window remains blank after Run in VisualAnalog (see Figure 12) is clicked, do the following:
If VisualAnalog indicates that the FIFO Capture timed out, do the following: