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~~NOTOC~~
====== Intel Reference Designs ======

====== Hardware ======
{{page>thirdparty}}

===== Add on Boards =====

==== BeMicro SDK/SDP Interposer ====

The [[https://www.arrow.com/en/products/adiinterposer/analog-devices/|System Demonstration Platform (SDP) Interposer]] connects various Analog Devices evaluation boards to Intel FPGAs found on the BeMicro SDK forming a hardware and software evaluation system. It’s designed for use with [[adi>sdp#exallist|ADI product evaluation boards]] and Circuits from the Lab™ [[adi>sdp#exallist|reference circuit evaluation boards]] that have the  [[/resources/eval/sdp/sdp-b/hardware_description#connector_pin_assignments|SDP connector]].

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^ Part Number / Purchase  ^  Description  ^ ADI Parts  ^
^ ^  Analog to Digital Converters  ^  ^
| [[adi>EVAL-AD7091SDZ]] | {{/resources/fpga/altera/bemicro/ad7091_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7091|ADI Reference Design]] \\ \\ The AD7091 is a 12-bit successive approximation register analog-to-digital converter (SAR ADC) that offers ultralow power consumption (typically 367 μA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). The AD7091 operates from a single 2.09 V to 5.25 V power supply. The AD7091 also features an on-chip conversion clock and a high speed serial interface. | [[adi>AD7091]] |
| [[adi>EVAL-AD7091RSDZ]] | {{/resources/fpga/altera/bemicro/ad7091r_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7091R|ADI Reference Design]] \\ \\ The AD7091R is a 12-bit successive approximation analog-to-digital converter (ADC) that offers ultralow power consumption (typically 349 µA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). Operating from a single 2.7 V to 5.25 V power supply, the part contains a wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 7 MHz. The AD7091R also features an on-chip conversion clock, accurate reference, and high speed serial interface. | [[adi>AD7091R]] |
| [[adi>EVAL-AD7176-2SDZ]] | {{/resources/fpga/altera/bemicro/ad7176_2_bemicro.jpg?150  }} **Reference Design:**  [[/resources/fpga/altera/bemicro/ad7176_2|ADI Reference Design]] \\ \\ The AD7176-2 is a fast settling, highly accurate, high resolution, multiplexed S-? analog-to-digital converter (ADC) for low band-width input signals. Its inputs can be configured as two fully differential or four pseudo differential inputs via the integrated crosspoint multiplexer. An integrated precision, 2.5 V, low drift (2 ppm/°C), band gap internal reference (with an output reference buffer) adds functionality and reduces the external component count. The maximum channel scan data rate is 50 kSPS (with a settling time of 20 µs), resulting in fully settled data of 17 noise free bits. User-selectable output data rates range from 5 SPS to 250 kSPS. The resolution increases at lower speeds. The AD7176-2 offers three key digital filters. The fast settling filter maximizes the channel scan rate. The Sinc3 filter maximizes the resolution for single-channel, low speed applications. For 50 Hz and 60 Hz environments, the AD7176-2 specific filter minimizes the settling times or maximizes the rejection of the line frequency. These enhanced filters enable simultaneous 50 Hz and 60 Hz rejec-tion with a 27 SPS output data rate (with a settling time of 36 ms). | [[adi>AD7176-2]] |
| [[adi>EVAL-AD7291SDZ]] | {{/resources/fpga/altera/bemicro/ad7291_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7291|ADI Reference Design]] \\ \\  The AD7291 is a 12-bit, low power, 8-channel, successive approximation analog-to-digital converter (ADC) with an internal temperature sensor. | [[adi>AD7291]] |
| [[adi>EVAL-AD7298SDZ]] | {{/resources/fpga/altera/bemicro/ad7298_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7298|ADI Reference Design]] \\ \\  The AD7298 is a 12-bit, high speed, low power, 8-channel, successive approximation ADC with an internal temperature sensor. The part operates from a single 3.3 V power supply and features throughput rates up to 1 MSPS. The device contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 30 MHz.     | [[adi>AD7298]] |
| [[adi>EVAL-AD7327SDZ]] | {{/resources/fpga/altera/bemicro/ad7327_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7327|ADI Reference Design]] \\ \\ The AD7327  is an 8-channel, 12-bit plus sign successive approximation ADC designed on the iCMOS™ (industrial CMOS) process. iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size. The AD7327 can accept true bipolar analog input signals. | [[adi>AD7327]] |
| [[adi>EVAL-AD7328SDZ]] | {{/resources/fpga/altera/bemicro/ad7328_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7328|ADI Reference Design]] \\ \\ The AD7328  is an 8-channel, 12-bit plus sign successive approximation ADC designed on the iCMOS™ (industrial CMOS) process. iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size. The AD7328 can accept true bipolar analog input signals. | [[adi>AD7328]] |
| [[adi>EVAL-AD7366SDZ]] | {{/resources/fpga/altera/bemicro/ad7366_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7366|ADI Reference Design]] \\ \\ The AD7366 is a dual 12-bit, high speed, low power, successive approximation analog-to-digital converter that feature throughput rates up to 1 MSPS. The device contains two ADCs, each preceded by a 2-channel multiplexer, and a low noise, wide bandwidth track-and-hold amplifier. The AD7366 is fabricated on the Analog Devices, Inc., industrial CMOS process (iCMOS), which is a technology platform combining the advantages of low and high voltage CMOS. The iCMOS process allows the AD7366 to accept high voltage bipolar signals in addition to reducing power consumption and package size. The AD7366 can accept true bipolar analog input signals in the ±10 V range, ±5 V range, and 0 V to 10 V range. | [[adi>AD7366]] |
| [[adi>EVAL-AD7367SDZ]] | {{/resources/fpga/altera/bemicro/ad7367_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7367|ADI Reference Design]] \\ \\ The AD7367 is a dual 14-bit, high speed, low power, successive approximation analog-to-digital converter that feature throughput rates up to 1 MSPS. The device contains two ADCs, each preceded by a 2-channel multiplexer, and a low noise, wide bandwidth track-and-hold amplifier. The AD7367 is fabricated on the Analog Devices, Inc., industrial CMOS process (iCMOS), which is a technology platform combining the advantages of low and high voltage CMOS. The iCMOS process allows the AD7367 to accept high voltage bipolar signals in addition to reducing power consumption and package size. The AD7367 can accept true bipolar analog input signals in the ±10 V range, ±5 V range, and 0 V to 10 V range. | [[adi>AD7367]] |
| [[adi>EVAL-AD7450ASDZ]] | {{/resources/fpga/altera/bemicro/ad7450a_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7450a|ADI Reference Design]] \\ \\ The AD7450A is  12-bit, high speed, low power, successive-approximation (SAR) analog-to-digital converter that feature a fully differential analog input. This part operates from a single 3 V or 5 V power supply and features throughput rates up to 1 MSPS. | [[adi>AD7450A]] |
| [[adi>EVAL-AD7490SDZ]] | {{/resources/fpga/altera/bemicro/ad7490_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7490|ADI Reference Design]] \\ \\ The AD7490 is a 12-bit high speed, low power, successive- approximation ADC. The part operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 1 MSPS. The part contains a low-noise, wide bandwidth track/hold amplifier that can handle input frequencies in excess of 1 MHz. | [[adi>AD7490]] |
| [[adi>EVAL-AD7492SDZ]] | {{/resources/fpga/altera/bemicro/ad7492_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7492|ADI Reference Design]] \\ \\ The AD7492 , AD7492-4, AD7492-5 are 12-bit high speed, low power, successive approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1.25 MSPS. They contain a low noise, wide bandwidth track/hold amplifier that can handle bandwidths up to 10 MHz. | [[adi>AD7492]] |
| [[adi>EVAL-AD7656-1SDZ]] | {{/resources/fpga/altera/bemicro/ad7656_1_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7656-1|ADI Reference Design]] \\ \\ The AD7656-1  is a reduced decoupling pin- and software-compatible version of AD7656. The AD7656-1 contains six 16-bit, fast, low power successive approximation ADC in a package designed on the iCMOS® process (industrial CMOS). iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. | [[adi>AD7656-1]] |
| [[adi>EVAL-AD7657-1SDZ]] | {{/resources/fpga/altera/bemicro/ad7657_1_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7657-1|ADI Reference Design]] \\ \\ The AD7657-1  is a reduced decoupling pin- and software-compatible version of AD7657. The AD7657-1 contains six 14-bit, fast, low power successive approximation ADC in a package designed on the iCMOS® process (industrial CMOS). iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. | [[adi>AD7657-1]] |
| [[adi>EVAL-AD7658-1SDZ]] | {{/resources/fpga/altera/bemicro/ad7658_1_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7658-1|ADI Reference Design]] \\ \\ The AD7658-1  is a reduced decoupling pin- and software-compatible version of AD7658. The AD7658-1 contains six 12-bit, fast, low power successive approximation ADC in a package designed on the iCMOS® process (industrial CMOS). iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. | [[adi>AD7658-1]] |
| [[adi>EVAL-AD7683SDZ]] | {{/resources/fpga/altera/bemicro/ad7683_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7683|ADI Reference Design]] \\ \\ The AD7683  is a  16-bit, 100 KSPS, charge redistribution, successive approximation, PulSAR® analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.7 V and 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes (B grade), an internal conversion clock, and a serial, SPI-compatible interface port. | [[adi>AD7683]] |
| [[adi>EVAL-AD7685SDZ]] | {{/resources/fpga/altera/bemicro/ad7685_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7685|ADI Reference Design]] \\ \\ The AD7685  is a 16-bit, 250kSPS, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN-. The reference voltage, REF, is applied externally and can be set up to the supply voltage. | [[adi>AD7685]] |
| [[adi>EVAL-AD7686SDZ]] | {{/resources/fpga/altera/bemicro/ad7686_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7686|ADI Reference Design]] \\ \\ The AD7686 is a 16-bit, 500 kSPS, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single 5V power supply. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN-. The reference voltage, REF, is applied externally and can be set up to the supply voltage. | [[adi>AD7686]] |
| [[adi>EVAL-AD7687SDZ]] | {{/resources/fpga/altera/bemicro/ad7687_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7687|ADI Reference Design]] \\ \\ The AD7687  is a 16-bit, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CNV rising edge, it samples the voltage difference between IN+ and IN- pins. The voltages on these pins usually swing in opposite phase between 0 V to REF. The reference voltage, REF, is applied externally and can be set up to the supply voltage. | [[adi>AD7687]] |
| [[adi>EVAL-AD7688SDZ]] | {{/resources/fpga/altera/bemicro/ad7688_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7688|ADI Reference Design]] \\ \\ The AD7688 is a 16-bit, 500 kSPS, charge redistribution successive-approximation Analog-to-Digital Converter which operates from a single 5V power supply, VDD. It contains a very low power high-speed 16-bit sampling ADC with no missing codes, an internal conversion clock and a versatile serial interface port. The part also contains a low noise, wide bandwidth, very short aperture delay track/hold circuit. On the CNV rising edge, it samples the voltage difference between IN+ and IN- pins. The voltages on these pins usually swing in opposite phase between 0 V to REF. The reference voltage REF is applied externally and can be set up to the supply voltage. | [[adi>AD7688]] |
| [[adi>EVAL-AD7690SDZ]] | {{/resources/fpga/altera/bemicro/ad7690_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7690|ADI Reference Design]] \\ \\ The AD7690 is an 18-bit, 400 kSPS successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 18-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. On the CNV rising edge, it samples the voltage difference between the IN+ and IN- pins. The voltages on these pins swing in opposite phase between 0 V and REF. The reference voltage, REF, is applied externally and can be set up to the supply voltage. | [[adi>AD7690]] |
| [[adi>EVAL-AD7691SDZ]] | {{/resources/fpga/altera/bemicro/ad7691_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7691|ADI Reference Design]] \\ \\ The AD7691 is an 18-bit, 250 kSPS successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 18-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. On the CNV rising edge, it samples the voltage difference between the IN+ and IN- pins. The voltages on these pins swing in opposite phase between 0 V and REF. The reference voltage, REF, is applied externally and can be set up to the supply voltage. | [[adi>AD7691]] |
| [[adi>EVAL-AD7693SDZ]] | {{/resources/fpga/altera/bemicro/ad7693_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7693|ADI Reference Design]] \\ \\ The AD7693 is a 16-bit, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single 5V power supply . It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN-. The reference voltage, REF, is applied externally and can be set up to the supply voltage. | [[adi>AD7693]] |
| [[adi>EVAL-AD7942SDZ]] | {{/resources/fpga/altera/bemicro/ad7942_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7942|ADI Reference Design]] \\ \\ The AD7942 is a 14-bit, charge redistribution, successive approximation PulSAR® ADC that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 14-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. On the CNV rising edge, it samples an analog input, IN+, between 0 V to VREF with respect to a ground sense, IN-. The reference voltage, VREF, is applied externally and is set up to be the supply voltage. Its power scales linearly with the throughput. | [[adi>AD7942]] |
| [[adi>EVAL-AD7946SDZ]] | {{/resources/fpga/altera/bemicro/ad7946_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7946|ADI Reference Design]] \\ \\ The AD7946 is a 14-bit, 500kSPS, charge redistribution, successive approximation ADC that operates from a single 5V power supply. It contains a very low power high-speed 14-bit sampling ADC with no missing codes, an internal conversion clock and a versatile serial interface port. The part also contains a low noise, wide bandwidth, very short aperture delay track/hold circuit. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN-. The reference voltage REF is applied externally and can be set up to the supply voltage. | [[adi>AD7946]] |
| [[adi>EVAL-AD7980SDZ]] | {{/resources/fpga/altera/bemicro/ad7980_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7980|ADI Reference Design]] \\ \\ The AD7980 is a 16-bit, successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 16-bit sampling ADC and a versatile serial interface port. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN-. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. Its power scales linearly with throughput. | [[adi>AD7980]] |
| [[adi>EVAL-AD7982SDZ]] | {{/resources/fpga/altera/bemicro/ad7982_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7982|ADI Reference Design]] \\ \\ The AD7982 is an 18-bit, successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 18-bit sampling ADC and a versatile serial interface port. On the CNV rising edge, the AD7982 samples the voltage difference between the IN+ and IN- pins. The voltages on these pins usually swing in opposite phases between 0 V and VREF. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. Its power scales linearly with throughput. | [[adi>AD7982]] |
| [[adi>EVAL-AD7983SDZ]] | {{/resources/fpga/altera/bemicro/ad7983_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7983|ADI Reference Design]] \\ \\ The AD7983 is a 16-bit, successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 16-bit sampling ADC and a versatile serial interface port. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN-. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. Its power scales linearly with throughput. | [[adi>AD7983]] |
| [[adi>EVAL-AD7984SDZ]] | {{/resources/fpga/altera/bemicro/ad7984_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7984|ADI Reference Design]] \\ \\ The AD7984 is an 18-bit, successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 18-bit sampling ADC and a versatile serial interface port. On the CNV rising edge, the AD7984 samples the voltage difference between the IN+ and IN- pins. The voltages on these pins usually swing in opposite phases between 0 V and VREF. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. | [[adi>AD7984]] |
| [[adi>AD7988-1 | EVAL-AD7988-1SDZ]] | {{/resources/fpga/altera/bemicro/ad7980_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7988-1|ADI Reference Design]] \\ \\ The AD7988-1/AD7988-5 are 16-bit, successive approximation, analog-to-digital converters (ADC) that operate from a single power supply, VDD. The AD7988-1 offers a 100 kSPS throughput, and the AD7988-5 offers a 500 kSPS throughput. They are low power, 16-bit sampling ADCs with a versatile serial interface port. On the CNV rising edge, they sample an analog input, IN+, between 0 V to VREF with respect to a ground sense, IN-. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. The SPI-compatible serial interface also features the ability to daisy-chain several ADCs on a single 3-wire bus using the SDI input. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate supply, VIO. The AD7988-1/AD7988-5 generics are housed in a 10-lead MSOP or a 10-lead LFCSP (QFN) with operation specified from -40°C to +125°C. | [[adi>AD7988-1]] |
| [[adi>AD7988-5 | EVAL-AD7988-5SDZ]] | {{/resources/fpga/altera/bemicro/ad7980_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7988-5|ADI Reference Design]] \\ \\ The AD7988-1/AD7988-5 are 16-bit, successive approximation, analog-to-digital converters (ADC) that operate from a single power supply, VDD. The AD7988-1 offers a 100 kSPS throughput, and the AD7988-5 offers a 500 kSPS throughput. They are low power, 16-bit sampling ADCs with a versatile serial interface port. On the CNV rising edge, they sample an analog input, IN+, between 0 V to VREF with respect to a ground sense, IN-. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. The SPI-compatible serial interface also features the ability to daisy-chain several ADCs on a single 3-wire bus using the SDI input. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate supply, VIO. The AD7988-1/AD7988-5 generics are housed in a 10-lead MSOP or a 10-lead LFCSP (QFN) with operation specified from -40°C to +125°C. | [[adi>AD7988-5]] |
^ ^  Digital to Analog Converters  ^  ^
| [[adi>EVAL-AD5415SDZ]] | {{/resources/fpga/altera/bemicro/ad5415_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5415|ADI Reference Design]] \\ \\ The AD5415 is a CMOS, 12-bit, dual channel, current output digital-to-analog converter. This device operates from a 2.5 V to 5.5 V power supply, making it suited to battery-powered applications and other applications. | [[adi>AD5415]] |
| [[adi>EVAL-AD5421SDZ]] | {{/resources/fpga/altera/bemicro/ad5421_-_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5421|ADI Reference Design]] \\ \\ The AD5421 is a complete, loop-powered, 4 mA to 20 mA digital-to-analog converter (DAC) designed to meet the needs of smart transmitter manufacturers in the industrial control industry. The DAC provides a high precision, fully integrated, low cost solution in a compact TSSOP package. | [[adi>AD5421]] |
| [[adi>EVAL-AD5449SDZ]] | {{/resources/fpga/altera/bemicro/ad5449_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5425|ADI Reference Design]] \\ \\ The AD5425 is a CMOS, 8-bit, current output digital-to-analog converter that operates from a 2.5 V to 5.5 V power supply, making it suitable for battery-powered applications and many other applications. | [[adi>AD5425]] |
| [[adi>EVAL-AD5443SDZ]] | {{/resources/fpga/altera/bemicro/ad5443_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5443|ADI Reference Design]] \\ \\ The AD5443 is a CMOS, 12-bit current output digital-to-analog converters (DACs), respectively. These devices operate from a 3 V to 5.5 V power supply, making them suitable for battery-powered applications and many other applications. | [[adi>AD5443]] |
| [[adi>EVAL-AD5446SDZ]] | {{/resources/fpga/altera/bemicro/ad5443_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5446|ADI Reference Design]] \\ \\ The AD5446 is a CMOS 14-bit current output, digital-to-analog converters (DACs). Operating from a single 2.5 V to 5.5 V power supply, these devices are suited for battery-powered and other applications. | [[adi>AD5446]] |
| [[adi>EVAL-AD5449SDZ]] | {{/resources/fpga/altera/bemicro/ad5449_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5449|ADI Reference Design]] \\ \\ The AD5449 is CMOS, 12-bit, dual-channel, current output digital-to-analog converter (DAC). This device operates from a 2.5 V to 5.5 V power supply, making it suited to battery-powered and other applications. | [[adi>AD5449]] |
| [[adi>EVAL-AD5453SDZ]] | {{/resources/fpga/altera/bemicro/ad5443_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5453|ADI Reference Design]] \\ \\ The AD5453 is a CMOS 14-bit current output digital-to-analog converters, respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suited to several applications, including battery- powered applications. | [[adi>AD5453]] |
| [[adi>EVAL-AD5541ASDZ]] | {{/resources/fpga/altera/bemicro/ad5541a_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5541A|ADI Reference Design]] \\ \\ The AD5541A is a single, 16-bit, serial input, unbuffered voltage output digital-to-analog converter (DAC) that operate from a single 2.7 V to 5.5 V supply.     | [[adi>AD5541A]] |
| [[adi>EVAL-AD5542ASDZ]] | {{/resources/fpga/altera/bemicro/ad5542a_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5542A|ADI Reference Design]] \\ \\ The AD5542A is single, 16-bit, serial input, unbuffered voltage output digital-to-analog converter (DAC) that operates from a single 2.7 V to 5.5 V supply. The DAC output range extends from 0 V to VREF and is guaranteed | [[adi>AD5542A]] |
| [[adi>EVAL-AD5543SDZ]] | {{/resources/fpga/altera/bemicro/ad5543_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5543|ADI Reference Design]] \\ \\ The AD5543 is precision 16-bit, low power, current output, small form factor digital-to-analog converter (DAC). It is designed to operate from a single 5 V supply with a ±10 V multiplying reference. | [[adi>AD5543]] |
| [[adi>EVAL-AD5543SDZ]] | {{/resources/fpga/altera/bemicro/ad5543_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5553|ADI Reference Design]] \\ \\ The AD5553 is precision 14-bit, low power, current output, small form factor digital-to-analog converter (DAC). It is designed to operate from a single 5 V supply with a ±10 V multiplying reference. | [[adi>AD5553]] |
| [[adi>EVAL-AD5570SDZ]] | {{/resources/fpga/altera/bemicro/ad5570_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5570|ADI Reference Design]] \\ \\ The AD5570 is a single 16-bit serial input, voltage output DAC that operates from supply voltages of ±11.4 V up to ±16.5 V. Integral linearity (INL) and differential nonlinearity (DNL) are accurate to 1 LSB. During power-up, when the supply voltages are changing, VOUT is clamped to 0 V via a low impedance path. | [[adi>AD5570]] |
| [[adi>EVAL-AD5629RSDZ]] | {{/resources/fpga/altera/bemicro/ad5629r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5629r|ADI Reference Design]] \\ \\ The AD5629R device is a low power, octal, 12-bit, buffered voltage-output DACs. It operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. | [[adi>AD5629R]] |
| [[adi>EVAL-AD5668]] | {{/resources/fpga/altera/bemicro/ad5668_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5668|ADI Reference Design]] \\ \\ The AD5668 device is a low power, octal, 16-bit, buffered voltage-output DAC. The device operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. | [[adi>AD5668]] |
| [[adi>EVAL-AD5669RSDZ]] | {{/resources/fpga/altera/bemicro/ad5669r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5669r|ADI Reference Design]] \\ \\ The AD5669R device is a low power, octal, 16-bit, buffered voltage-output DACs. It operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. | [[adi>AD5669R]] |
| [[adi>EVAL-AD5684RSDZ]] | {{/resources/fpga/altera/bemicro/ad5686r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5684r|ADI Reference Design]] \\ \\ The AD56849R is a low power, quad, 12-bit buffered voltage output DACs. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The EVAL-AD5684R evaluation board is designed to help customers quickly prototype new AD5684R circuits and reduce design time. The board requires ±5 V supplies. These are used to power the output amplifier and Vref. | [[adi>AD5684R]] |
| [[adi>EVAL-AD5686RSDZ]] | {{/resources/fpga/altera/bemicro/ad5686r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5686r|ADI Reference Design]] \\ \\ The AD5686R  is a low power, quad, 16-bit buffered voltage output DACs. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The EVAL-AD5686R evaluation board is designed to help customers quickly prototype new AD5686R circuits and reduce design time. The board requires ±5 V supplies. These are used to power the output amplifier and Vref. | [[adi>AD5686R]] |
| [[adi>EVAL-AD5694RSDZ]] | {{/resources/fpga/altera/bemicro/ad5694r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5694r|ADI Reference Design]] \\ \\ The AD5694R  nanoDAC is a quad, 12-bit, rail-to-rail, voltage output DAC. The device includes a 2.5V, 2ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5V (gain=1) or 5V (gain=2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design and exhibits less than 0.1% FSR gain error and 1.5mV offset error performance. | [[adi>AD5694R]] |
| [[adi>EVAL-AD5696RSDZ]] | {{/resources/fpga/altera/bemicro/ad5696r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5696r|ADI Reference Design]] \\ \\ The AD5696R  nanoDAC is a quad, 16-bit, rail-to-rail, voltage output DAC. The device includes a 2.5V, 2ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5V (gain=1) or 5V (gain=2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design and exhibits less than 0.1% FSR gain error and 1.5mV offset error performance. | [[adi>AD5696R]] |
| [[adi>EVAL-AD5755SDZ]] | {{/resources/fpga/altera/bemicro/ad5755_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5755|ADI Reference Design]] \\ \\ The AD5755 is a quad, voltage and current output DAC that operates with a power supply range from -26.4 V to +33 V. On-chip dynamic power control minimizes package power dissipation in current mode. This is achieved by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on chip power dissipation. | [[adi>AD5755]] |
| [[adi>EVAL-AD5755-1SDZ]] | {{/resources/fpga/altera/bemicro/ad5755_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5755|ADI Reference Design]] \\ \\ The AD5755-1 is a quad, voltage and current output DAC, that operates with a power supply range from -26.4 V to +33 V. On chip dynamic power control minimizes package power dissipation in current mode. This is achieved by regulating the voltage on the output driver from between 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5755-1. | [[adi>AD5755-1]] |
| [[adi>EVAL-AD5757SDZ]] | {{/resources/fpga/altera/bemicro/ad5757_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5757|ADI Reference Design]] \\ \\ The AD5757 is a quad, current output DAC that operates with a power supply range from 10.8 V to 33 V. On-chip dynamic power control minimizes package power dissipation by regulat-ing the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. | [[adi>AD5757]] |
| [[adi>EVAL-AD5760SDZ|EVAL-AD5760SDZ]] | {{/resources/fpga/altera/bemicro/ad5760_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5760|ADI Reference Design]] \\ \\ The AD5760 is a true 16-bit, unbuffered voltage out Dac that operates from a bipolar supply up to 33V. Both reference inputs are buffered on chip and external buffers are not required. The AD5760 accepts a positive reference input in the range of 5V to VDD – 2.5V and a negative reference input in the range of VSS + 2.5v to 0V. The AD5760 offers relative accuracy of +/-0.5 LSB max and operation is guaranteed monotonic with a ±0.5 LSB DNL max range specification. | [[adi>AD5760]] |
| [[adi>EVAL-AD5780SDZ]] | {{/resources/fpga/altera/bemicro/ad5780_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5780|ADI Reference Design]] \\ \\ The AD5780 is a true 18-bit, unbuffered voltage out DAC that operates from a bipolar supply up to 33V. Both reference inputs are buffered on chip and external buffers are not required.The AD5780 accepts a positive reference input in the range of 5V to VDD – 2.5V and a negative reference input in the range of VSS + 2.5v to 0V. The AD5780 offers relative accuracy of +/-1 LSB max and operation is guaranteed monotonic with a ±1 LSB DNL max range specification. | [[adi>AD5780]] |
| [[adi>EVAL-AD5781SDZ]] | {{/resources/fpga/altera/bemicro/ad5781_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5781|ADI Reference Design]] \\ \\ The AD5781 is a single 18-bit, unbuffered voltage-output DAC that operates from a bipolar supply of up to 33 V. The AD5781 accepts a positive reference input in the range 5V to VDD – 2.5 V and a negative reference input in the range VSS + 2.5 V to 0 V. The AD5781 offers a relative accuracy specification of ±0.5 LSB max, and operation is guaranteed monotonic with a ±0.5 LSB DNL max specification. | [[adi>AD5781]] |
| [[adi>EVAL-AD5790SDZ]] | {{/resources/fpga/altera/bemicro/ad5790_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5790|ADI Reference Design]] \\ \\ The AD5790 is a single 20-bit, voltage out DAC that operates from a bipolar supply up to 33V. Reference buffers are also provided on-chip. The AD5790 accepts a positive reference input in the range of 5V to VDD – 2.5V and a negative reference input in the range of VSS + 2.5v to 0V. The AD5790 offers a relative accuracy of +/-2 LSB's max and operation is guaranteed monotonic with a -1 LSB to +3 LSB's DNL specification. | [[adi>AD5790]] |
| [[adi>EVAL-AD5791SDZ]] | {{/resources/fpga/altera/bemicro/ad5791_-_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5791|ADI Reference Design]] \\ \\ The AD5791 is a single 20-bit, unbuffered voltage-output DAC that operates from a bipolar supply of up to 33 V. The AD5791 accepts a positive reference input in the range 5 V to VDD – 2.5V and a negative reference input in the range VSS + 2.5 V to 0 V. The AD5791 offers a relative accuracy specification of ±1 LSB max, and operation is guaranteed monotonic with a ±1 LSB DNL max specification. | [[adi>AD5791]] |
^ ^  Digital Potentiometers  ^  ^
| [[adi>EVAL-ADN2850SDZ]] | {{/resources/fpga/altera/bemicro/ad2850_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/adn2850|ADI Reference Design]] \\ \\ The ADN2850 is a dual-channel, nonvolatile memory, digitally controlled resistors with 1024-step resolution, offering guaranteed maximum low resistor tolerance error of ±8%. The device performs the same electronic adjustment function as a mechanical rheostat with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. The versatile programming of the ADN2850 via an SPI®-compatible serial interface allows 16 modes of operation and adjustment including scratchpad programming, memory storing and restoring, increment/decrement, ±6 dB/step log taper adjustment, wiper setting readback, and extra EEMEM for user-defined information such as memory data for other components, look-up table, or system identification information. | [[adi>ADN2850]] |
| [[adi>EVAL-AD5110SDZ]] | {{/resources/fpga/altera/bemicro/ad5110_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5110|ADI Reference Design]] \\ \\ The AD5110 provides a nonvolatile solution for 128-/64-/32-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W pins. The low resistor tolerance, low nominal temperature coefficient and high bandwidth simplify open-loop applications, as well as tolerance matching applications. The new low wiper resistance feature minimizes the wiper resistance in the extremes of the resistor array to only 45 O, typical. The wiper settings are controllable through an I2C-compatible digital interface that is also used to readback the wiper register and EEPROM content. Resistor tolerance is stored within EEPROM, providing an end-to-end tolerance accuracy of 0.1%. | [[adi>AD5110]] |
| [[adi>EVAL-AD5111SDZ]] | {{/resources/fpga/altera/bemicro/ad5110_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5111|ADI Reference Design]] \\ \\ The AD5111 provides a nonvolatile solution for 128-/64-/32-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W pins. The low resistor tolerance, low nominal temperature coefficient, and high bandwidth simplify open-loop applications, as well as tolerance matching applications. The new low wiper resistance feature minimizes the wiper resistance in the extremes of the resistor array to only 45 O, typical. A simple 3-wire up/down interface allows manual switching or high speed digital control with clock rates up to 50 MHz. | [[adi>AD5111]] |
| [[adi>EVAL-AD5162SDZ]] | {{/resources/fpga/altera/bemicro/ad5162_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5162|ADI Reference Design]] \\ \\ The AD5162  provides a compact 3 mm x 4.9 mm packaged solution for dual 256 position adjustment applications. This device performs the same electronic adjustment function as a 3-terminal mechanical potentiometer. Available in four different end-to-end resistance values (2.5 kO, 10 kO, 50 kO, 100 kO), this low temperature coefficient device is ideal for high accuracy and stability-variable resistance adjustments. | [[adi>AD5162]] |
| [[adi>EVAL-AD5172SDZ]] | {{/resources/fpga/altera/bemicro/ad5172_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5172|ADI Reference Design]] \\ \\ The AD5172/AD5173 are dual-channel, 256-position, one-time programmable (OTP) digital potentiometers that employ fuse link technology to achieve memory retention of resistance settings. OTP is a cost-effective alternative to EEMEM for users who do not need to program the digital potentiometer setting in memory more than once. These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. | [[adi>AD5172]] |
| [[adi>EVAL-AD5232SDZ]] | {{/resources/fpga/altera/bemicro/ad5232_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5232|ADI Reference Design]] \\ \\ The AD5232 device provides a nonvolatile, dual-channel, digitally controlled variable resistor (VR) with 256-position resolution. This device performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. The versatile programming of the AD5232, performed via a microcontroller, allows multiple modes of operation and adjustment. | [[adi>AD5232]] |
| [[adi>EVAL-AD5235SDZ]] | {{/resources/fpga/altera/bemicro/ad5235_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5235|ADI Reference Design]] \\ \\ The AD5235 is a dual-channel, nonvolatile memory, digitally controlled potentiometer with 1024-step resolution, offering guaranteed maximum low resistor tolerance error of ±8%. The device performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. The versatile programming of the AD5235 via an SPI®-compatible serial interface allows 16 modes of operation and adjustment including scratchpad programming, memory storing and restoring, increment/decrement, ±6 dB/step log taper adjustment, wiper setting readback, and extra EEMEM for user-defined information such as memory data for other components, look-up table, or system identification information. | [[adi>AD5235]] |
| [[adi>EVAL-AD5252SDZ]] | {{/resources/fpga/altera/bemicro/ad5252_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5252|ADI Reference Design]] \\ \\ The AD5252 is a dual channel, digitally controlled variable resistor (VR) with resolutions of 256 positions. This device performs the same electronic adjustment function as a potentiometer or variable resistor. The AD5252’s versatile programming via a Micro Controller allows multiple modes of operation and adjustment. | [[adi>AD5252]] |
| [[adi>EVAL-AD5254SDZ]] | {{/resources/fpga/altera/bemicro/ad5254_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5254|ADI Reference Design]] \\ \\ The AD5254 is quad-channel, I2C, nonvolatile memory, digitally controlled potentiometers with 256 positions, respectively. This device performs the same electronic adjustment functions as mechanical potentiometers, trimmers, and variable resistors. | [[adi>AD5254]] |
| [[adi>EVAL-AD5270SDZ]] | {{/resources/fpga/altera/bemicro/ad5270_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5270|ADI Reference Design]] \\ \\ The AD5270 is single-channel, 1024-position digital rheostat that combines industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package.  | [[adi>AD5270]] |
| [[adi>EVAL-AD5272SDZ]] | {{/resources/fpga/altera/bemicro/ad5272_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5272|ADI Reference Design]] \\ \\ The AD5272 is single-channel, 1024-position digital rheostat that combines industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. | [[adi>AD5272]] |
| [[adi>EVAL-AD8403SDZ]] | {{/resources/fpga/altera/bemicro/ad8403_-_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad8403|ADI Reference Design]] \\ \\ The AD8403 provides a quad channel, 256 position digitally controlled variable resistor (VR) device. This device performs the same electronic adjustment function as a potentiometer or variable resistor. The AD8403 contains four independent variable resistors in 24-lead PDIP, SOIC and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 1 kO, 10 kO, 50 kO or 100 kO has a ±1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-before-make operation. | [[adi>AD8403]] |
^ ^  Direct Digital Synthesis ( DDS) & Modulators  ^  ^
| [[adi>EVAL-AD9833SDZ]] | {{/resources/fpga/altera/bemicro/ad9833_-_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad9833|ADI Reference Design]] \\ \\ The AD9833 is a low power, programmable waveform generator capable of producing sine, triangular, and square wave outputs. Waveform generation is required in various types of sensing, actuation, and time domain reflectometry (TDR) applications. The output frequency and phase are software programmable, allowing easy tuning. No external components are needed. The frequency registers are 28 bits; with a 25 MHz clock rate, resolution of 0.1 Hz can be achieved. Similarly, with a 1 MHz clock rate, the AD9833 can be tuned to 0.004 Hz resolution. | [[adi>AD9833]] |
| [[adi>EVAL-AD9834SDZ]] | {{/resources/fpga/altera/bemicro/ad9834_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad9834|ADI Reference Design]] \\ \\ The AD9834 is a 75 MHz low power DDS device capable of producing high performance sine and triangular outputs. It also has an on-board comparator that allows a square wave to be produced for clock generation. Consuming only 20 mW of power at 3 V makes the AD9834 an ideal candidate for power-sensitive applications. | [[adi>AD9834]] |
| [[adi>EVAL-AD9837SDZ]] | {{/resources/fpga/altera/bemicro/ad9837_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad9837|ADI Reference Design]] \\ \\ The AD9837 is a low power, programmable waveform generator capable of producing sine, triangular, and square wave outputs. Waveform generation is required in various types of sensing, actuation, and time domain reflectometry (TDR) applications. The output frequency and phase are software programmable, allowing easy tuning. The frequency registers are 28 bits: with a 16 MHz clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz clock rate, the AD9837 can be tuned to 0.02 Hz resolution. | [[adi>AD9837]] |
| [[adi>EVAL-AD9838SDZ]] | {{/resources/fpga/altera/bemicro/ad9838_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad9838|ADI Reference Design]] \\ \\ The AD9838 is a low power DDS device capable of producing high performance sine and triangular outputs. It also has an on-board comparator that allows a square wave to be produced for clock generation. Consuming only 11 mW of power at 2.3 V the AD9838 is an ideal candidate for power-sensitive applications. | [[adi>AD9838]] |
^ ^  MEMS Microphones  ^  ^
| [[adi>EVAL-ADMP441Z|EVAL-ADMP441Z]] | {{/resources/fpga/altera/bemicro/admp441_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/admp441|ADI Reference Design]] \\ \\ The ADMP441 is a high performance, low power, digital output, omnidirectional MEMS microphone with a bottom port. The complete ADMP441 solution consists of a MEMS sensor, signal conditioning, an analog-to-digital converter, antialiasing filters, power management, and an industry standard 24-bit I2S inter-face. The I2S interface allows the ADMP441 to connect directly to digital processors, such as DSPs and microcontrollers, with-out the need for an audio codec in the system. The ADMP441 has a high SNR and high sensitivity, making it an excellent choice for far field applications. The ADMP441 has a flat wideband frequency response, resulting in natural sound with high intelligibility. A built-in particle filter provides high reliability. | [[adi>ADMP441]] |
^ ^  PLL Synthesizers / VCOs  ^  ^
| [[adi>EVAL-ADF4001|EVAL-ADF4001SD1Z]] | {{/resources/fpga/altera/bemicro/adf4001_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/adf4001|ADI Reference Design]] \\ \\ The ADF4001 frequency synthesizer can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator) or VCXO (Voltage Controlled Crystal Oscillator). The N min value of 1 allows flexibility in clock generation. | [[adi>ADF4001]] |
| [[adi>EVAL-ADF4002|EVAL-ADF4002SD1Z]] | {{/resources/fpga/altera/bemicro/adf4002_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/adf4002|ADI Reference Design]] \\ \\ The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R & N to 1, the part can be used as a stand alone PFD and charge pump. | [[adi>ADF4002]] |
| [[adi>EVAL-ADF4106|EVAL-ADF4106SD1Z]] | {{/resources/fpga/altera/bemicro/adf4106_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/adf4106|ADI Reference Design]] \\ \\ The ADF4106 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A counter and B counter, and a dual-modulus prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. | [[adi>ADF4106]] |
| [[adi>EVAL-ADF4156|EVAL-ADF4156SD1Z]] | {{/resources/fpga/altera/bemicro/adf4156_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/adf4156|ADI Reference Design]] \\ \\ The ADF4156 is a 6.2 GHz fractional-N frequency synthesizer that implements local oscillators in the upconversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a S-? based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter. | [[adi>ADF4156]] |
| [[adi>EVAL-ADF4157|EVAL-ADF4157SD1Z]] | {{/resources/fpga/altera/bemicro/adf4157_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/adf4157|ADI Reference Design]] \\ \\ The ADF4157 is a 6 GHz fractional-N frequency synthesizer with a 25-bit fixed modulus, allowing subhertz frequency resolution at 6 GHz. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a S-? based fractional interpolator to allow programmable fractional-N division. The INT and FRAC values define an overall N divider, N = INT + (FRAC/225). The ADF4157 features cycle slip reduction circuitry, which leads to faster lock times without the need for modifications to the loop filter. | [[adi>ADF4157]] |
^ ^  Synchro/Resolver to Digital Converters  ^  ^
| [[adi>EVAL-AD2S1205]] | {{/resources/fpga/altera/bemicro/ad2s1205_bemicro.jpg?150  }} **Reference Design:** [[resources/fpga/altera/bemicro/ad2s1205|ADI Reference Design]] \\ \\ The AD2S1205 is a complete 12-bit resolution tracking resolver-to-digital converter that contains an on-board programmable sinusoidal oscillator providing sine wave excitation for resolvers. The converter accepts 3.15 V p-p ± 27% input signals on the Sin and Cos inputs. A Type II tracking loop is employed to track the inputs and convert the input Sin and Cos information into a digital representation of the input angle and velocity. The maximum tracking rate is a function of the external clock frequency. The performance of the AD2S105 is specified across a frequency range of 8.192 MHz ± 25%, allowing a maximum tracking rate of 1250 rps.  |  [[adi>AD2S1205]]  |
^ ^  Circuits from the Lab  ^  ^
| [[adi>EVAL-CN0150A-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0150_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0150|ADI Reference Design]] \\ \\  This circuit measures RF power at any frequency from 1 MHz to 8 GHz over a range of approximately 60 dB. The measurement result is provided as a digital code at the output of a 12-bit ADC with serial interface and integrated reference. The output of the RF detector has a glueless interface to the ADC and uses most of the ADC’s input range without further adjustment. A simple two-point system calibration is performed in the digital domain. | [[adi>CN0150]] |
| [[adi>EVAL-CN0178-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0178_bemicro.png?150  }} **Reference Design:**  [[/resources/fpga/altera/bemicro/cn0178|ADI Reference Design]] \\ \\ This circuit uses the ADL5902 TruPwr™ detector to measure the rms signal strength of RF signals with varying crest factors (peak-to-average ratio) over a dynamic range of approximately 65 dB and operates at frequencies from 50 MHz up to 9 GHz. | [[adi>CN0178]] |
| [[adi>EVAL-CN0187-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0187_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0187|ADI Reference Design]] \\ \\ This circuit measures peak and rms power at any RF frequency from 450 MHz to 6 GHz over a range of approximately 45 dB. The measurement results are converted to differential signals in order to eliminate noise and are provided as digital codes at the output of a 12-bit SAR ADC with serial interface and integrated reference. A simple twopoint calibration is performed in the digital domain. | [[adi>CN0187]] |
| [[adi>EVAL-CN0188-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0188_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0188|ADI Reference Design]] \\ \\ This circuit monitors current in individual channels of -48 V to better than 1% accuracy. The load current passes through a shunt resistor, which is external to the circuit. The shunt resistor value is chosen so that the shunt voltage is approximately 50 mV at maximum load current. | [[adi>CN0188]] |
| [[adi>EVAL-CN0189-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0189.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0189|ADI Reference Design]] \\ \\ The CN-0189 circuit incorporates a dual axis ADXL203 accelerometer and the AD7887 12-bit successive approximation (SAR) ADC to create a dual axis tilt measurement system. Acceleration in the X or Y axis will produce a corresponding output voltage on the XOUT or YOUT output pins of the device. The AD8608 quad op amp buffers, attenuates, and level shifts the ADXL203 outputs so they are at the proper levels to drive the inputs of the AD7887. The rail-to-rail input/output AD8608 is chosen for its low offset voltage , low bias current , low noise , and small footprint . The AD7887 is configurable for either dual or single channel operation via the on-chip control register. In this application it is configured for dual channel mode, allowing the user to monitor both outputs of the ADXL203, thereby providing a more accurate and complete solution. | [[adi>CN0189]] |
| [[adi>EVAL-CN0194-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0194_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0194|ADI Reference Design]] \\ \\ This circuit provides galvanic isolation for high speed, high accuracy, simultaneous sampling analog-todigital conversion applications. The 16-bit AD7685 PulSAR ADC is versatile and allows monitoring of multiple channels through daisy chaining. An input circuit based on the AD8615 op amp level shifts, attenuates, and buffers a ±10 V industrial signal to match the input requirements of the ADC. The flexible circuit includes a precision ADR391 reference and two quadchannel ADuM1402 digital isolators to provide a compact and cost effective solution to a popular industrial data acquisition application. | [[adi>CN0194]] |
| [[adi>EVAL-CN0202-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0202_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0202|ADI Reference Design]] \\ \\ The EVAL-CN0202-SDPZ board provides a full function, flexible, programmable analog output solution that meets most requirements for programmable logic controller (PLC) and distributed control system (DCS) applications. | [[adi>CN0202]] |
| [[adi>EVAL-CN0203-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0203_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0203|ADI Reference Design]] \\ \\ The EVAL-CN0203-SDPZ board provides a full function, flexible, programmable analog output solution with only two analog components and meets most requirements for programmable logic controller (PLC) and distributed control system (DCS) applications. | [[adi>CN0203]] |
| [[adi>EVAL-CN0204-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0204_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0204|ADI Reference Design]] \\ \\ This circuit provides a full function, high voltage (up to 44 V), flexible, programmable analog output solution that meets most requirements for programmable logic controller (PLC) and distributed control system (DCS) applications. | [[adi>CN0204]] |
| [[adi>EVAL-CN0209-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0209_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0209|ADI Reference Design]] \\ \\ This circuit provides a fully programmable universal analog front end (AFE) for process control applications. The following inputs are supported: 2-, 3-, and 4- wire RTD configurations, thermocouple inputs with cold junction compensation, unipolar and bipolar input voltages, and 4 mA-to-20 mA inputs. | [[adi>CN0209]] |
| [[adi>EVAL-CN0216-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0216_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0216|ADI Reference Design]] \\ \\ This circuit is a precision weigh scale signal conditioning system. It uses the AD7791, a low power buffered 24-bit sigma-delta ADC along with two external ADA4528-1 zero-drift amplifiers. This solution allows for high dc gain with a single supply. | [[adi>CN0216]] |
| [[adi>EVAL-CN0218-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0218_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0218|ADI Reference Design]] \\ \\ This circuit monitors current in systems with high positive common-mode dc voltages of up to +500 V with less than 0.2% error. The load current passes through a shunt resistor, which is external to the circuit. The shunt resistor value is chosen so that the shunt voltage is approximately 500 mV at maximum load current. | [[adi>CN0218]] |
| [[adi>EVAL-CN0235-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0235_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0235|ADI Reference Design]] \\ \\ The circuit from the EVAL-CN0235-SDPZ board is a fully isolated lithium ion battery monitoring and protection system. Lithium ion (Li-Ion) battery stacks contain a large number of individual cells that must be monitored correctly in order to enhance the battery efficiency, prolong the battery life, and ensure safety. | [[adi>CN0235]] |
| [[adi>EVAL-CN0240-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0240_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0240|ADI Reference Design]] \\ \\ The circuit from the **EVAL-CN0240-SDPZ** board monitors bidirectional current from sources with dc voltages of up to ±270V with less than 1% linearity error. The load current passes through a shunt resistor, which is external to the circuit. The shunt resistor value is chosen so that the shunt voltage is approximately 100 mV at maximum load current. | [[adi>CN0240]] |
| [[adi>EVAL-CN0241-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0241_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0241|ADI Reference Design]] \\ \\ The circuit from the EVAL-CN0241-SDPZ board is a classic high-side current sensing circuit topology with a single sense resistor. High-side current monitors are likely to encounter overvoltage conditions from transients or when the monitoring circuits are connected, disconnected, or powered down. | [[adi>CN0241]] |
| [[adi>EVAL-CN0271-SDPZ]] | {{/resources/fpga/altera/bemicro/cn0271_bemicro.jpg?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/cn0271|ADI Reference Design]] \\ \\ The circuit from the EVAL-CN0271-SDPZ board is a complete thermocouple signal conditioning circuit with cold junction compensation followed by a 16-bit sigma-delta (S-?) analog-to-digital converter (ADC). | [[adi>CN0271]] |
==== CED1Z ====

The [[adi>EVAL-CED | CED1Z]] board is part of a next generation platform from Analog Devices Inc., intended for use in evaluation,
demonstration and development of systems using Analog Devices precision converters. It provides the necessary
communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link.

|< 100% 15% 75% 10% >|
^ Part Number / Purchase  ^  Description  ^ ADI Parts  ^
| [[adi>EVAL-AD7262EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7262.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7262|ADI Reference Design]] \\ \\ The AD7262 are dual, 12-bit, high speed, low power, successive approximation ADCs that operate from a single 5 V power supply. The AD7262 features throughput rates of up to 1 MSPS per on-chip ADC. Two complete ADC functions allow simultaneous sampling and conversion of two channels. Each ADC is preceded by a true differential analog input with a PGA. There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128.| [[adi>AD7262]] |
| [[adi>EVAL-AD7400EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7400a.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7400a|ADI Reference Design]] \\ \\ The AD7400 is a second-order, sigma-delta modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7400 operates from a 5 V power supply and accepts a differential input signal of ±200 mV (±320 mV full scale). The analog input is sampled continuously by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 10 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). | [[adi>AD7400]] |
| [[adi>EVAL-AD7400AEDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7400a.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7400a|ADI Reference Design]] \\ \\ The AD7400A is a second-order, sigma-delta modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7400A operates from a 5 V power supply and accepts a differential input signal of ±250 mV (±320 mV full scale). The analog input is sampled continuously by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 10 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). | [[adi>AD7400A]] |
| [[adi>EVAL-AD7401EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7401.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7401|ADI Reference Design]] \\ \\ The AD7401 is a second-order, sigma-delta modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7401 operates from a 5 V power supply and accepts a differential input signal of ±200 mV (±320 mV full scale). The analog input is sampled continuously by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 20 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). | [[adi>AD7401]] |
| [[adi>EVAL-AD7401AEDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7401.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7401|ADI Reference Design]] \\ \\ The AD7401A is a second-order, sigma-delta modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7401A operates from a 5 V power supply and accepts a differential input signal of ±250 mV (±320 mV full scale). The analog input is sampled continuously by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 20 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). | [[adi>AD7401A]] |
| [[adi>EVAL-AD7606EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7606.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7606|ADI Reference Design]] \\ \\ The AD7606 is a 16-bit, 8 channel, simultaneous sampling Analog-to-Digital Data Acquisition system (DAS). The part contains analog input clamp protection, 2nd order anti-alias filter, track and hold amplifier, 16-bit charge redistribution successive approximation ADC, flexible digital filter, 2.5V reference and reference buffer and high speed serial and parallel interfaces.    | [[adi>AD7606]] |
| [[adi>EVAL-AD7606-4EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7606.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7606|ADI Reference Design]] \\ \\ The AD7606-4 is a 16-bit, 4 channel, simultaneous sampling Analog-to-Digital Data Acquisition system (DAS). The part contains analog input clamp protection, 2nd order anti-alias filter, track and hold amplifier, 16-bit charge redistribution successive approximation ADC, flexible digital filter, 2.5V reference and reference buffer and high speed serial and parallel interfaces. | [[adi>AD7606-4]] |
| [[adi>EVAL-AD7606-6EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7606.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7606|ADI Reference Design]] \\ \\ The AD7606-6 is a 16-bit, 6 channel, simultaneous sampling Analog-to-Digital Data Acquisition system (DAS). The part contains analog input clamp protection, 2nd order anti-alias filter, track and hold amplifier, 16-bit charge redistribution successive approximation ADC, flexible digital filter, 2.5V reference and reference buffer and high speed serial and parallel interfaces. | [[adi>AD7606-6]] |
| [[adi>EVAL-AD7621EDZ]] | {{/resources/fpga/altera/cedz/img_0024.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7621|ADI Reference Design]] \\ \\ The AD7621 is a 16-bit, 3 MSPS, charge redistribution SAR, fully differential analog-to-digital converter that operates from a single 2.5 V power supply. The part contains a high-speed 16-bit sampling ADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports. | [[adi>AD7621]] |
| [[adi>EVAL-AD7626EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7626.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7626|ADI Reference Design]] \\ \\ The AD7626 is a 16-bit, 10 MSPS, charge redistribution successive approximation register (SAR) based architecture analog-to-digital converter (ADC). SAR architecture allows unmatched performance both in noise (91.5 dB SNR) and in linearity (±0.45 LSB INL). The AD7626 contains a high speed, 16-bit sampling ADC, an internal conversion clock, and an internal buffered reference. On the CNV edge, it samples the voltage difference between the IN+ and IN- pins. The voltages on these pins swing in opposite phase between 0 V and REF. The 4.096 V reference voltage, REF, can be generated internally or applied externally. | [[adi>AD7626]] |
| [[adi>EVAL-AD7671EDZ]] | {{/resources/fpga/altera/cedz/img_0024.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7671|ADI Reference Design]] \\ \\ Pushing the speed limit of the breakthrough PulSAR™ core, the AD7671 is a 16-bit, 1 MSPS, charge redistribution SAR Analog-to-Digital Converter that operates from a single 5 V power supply. It contains a high-speed 16-Bit sampling ADC, a resistor input scalar, which allows various input ranges, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. | [[adi>AD7671]] |
| [[adi>EVAL-AD7682EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7682.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7682|ADI Reference Design]] \\ \\ The AD7682 is a 4-channel, 16-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) that operates from a single power supply. The AD7682 contains all components for use in a multichannel, low power data acquisition system, including a true 16-bit SAR ADC with no missing codes; an 4-channel, low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order. | [[adi>AD7682]] |
| [[adi>EVAL-AD7689EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7689.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7689|ADI Reference Design]] \\ \\ The AD7689 is a 8-channel, 16-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) that operates from a single power supply. The AD7689 contains all components for use in a multichannel, low power data acquisition system, including a true 16-bit SAR ADC with no missing codes; an 8-channel, low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order. | [[adi>AD7689]] |
| [[adi>EVAL-AD7699EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7699.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7699|ADI  Reference Design]] \\ \\ The AD7699 is a 8-channel, 16-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) that operates from a single power supply. The AD7699 contains all components for use in a multichannel, low power data acquisition system, including a true 16-bit SAR ADC with no missing codes; an 8-channel, low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order. | [[adi>AD7699]] |
| [[adi>EVAL-AD7763EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7763.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7763|ADI Reference Design]] \\ \\ The AD7763 high performance, 24-bit, Σ-Δ analog-to-digital converter (ADC) combines wide input bandwidth and high speed with the benefits of Σ-Δ conversion, as well as performance of 107 dB SNR at 625 kSPS, making it ideal for high speed data acquisition. An integrated buffer to drive the reference, a differential amplifier for signal buffering and level shifting, an overrange flag, internal gain and offset registers, and a low-pass, digital FIR filter make the AD7763 a compact, highly integrated data acquisition device requiring minimal peripheral component selection. | [[adi>AD7763]] |
| [[adi>EVAL-AD7766-1EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7766.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7766|ADI Reference Design]] \\ \\ The AD7766-1 is a high performance 24-bit oversampled SAR analog-to-digital converter (ADC). TheAD7766-1 combines the benefits of a large dynamic range and input bandwidth, consuming 10.5 mW power, contained in a 16-lead TSSOP package. | [[adi>AD7766]] |
| [[adi>EVAL-AD7938CBZ]] | {{/resources/fpga/altera/ced1z/img_0024.png?150  }} **Reference Design:**[[/resources/fpga/altera/ced1z/ad7938|ADI Reference Design]] \\ \\ The AD7938 is 12-bit, high speed, low power, successive approximation (SAR) analog-to-digital converter (ADC). The part operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 1.5 MSPS. The part contains a low noise, wide bandwidth, differential track-and-hold amplifier that can handle input frequencies up to 50 MHz. | [[adi>AD7938]] |
| [[adi>EVAL-ADAS3022EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_adas3022.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/adas3022|ADI Reference Design]] \\ \\ The ADAS3022 is a complete 16-bit, 1MSPS analog to digital data acquisition system. The part includes an 8 channel low leakage multiplexer, high common mode rejection programmable differential gain stage, a precision low drift 4.096V reference and buffer, and a 16-bit charge redistribution successive approximation register (SAR) architecture analog-to-digital converter (ADC). | [[adi>ADAS3022]] |
| [[adi>EVAL-ADAS3023EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_adas3022.png?150  }} **Reference Design:** [[/resources/fpga/altera/ced1z/adas3023|ADI Reference Design]] \\ \\ The ADAS3023 is a complete 16-bit successive approximation based analog-to-digital data acquisition system. This device is capable of simultaneously sampling up to 500 kSPS for two channels, 250 kSPS for four channels, 167 kSPS for six channels, and 125 kSPS for eight channels manufactured on the Analog Devices, Inc., proprietary iCMOS® high voltage industrial process technology. | [[adi>ADAS3023]] |
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